Inspection system, inspection method, and method for manufacturing semiconductor device

• US 7,112,952 B2
• Filed: 01/27/2005
• Issued: 09/26/2006
• Est. Priority Date: 01/30/2004
• Status: Expired due to Fees

• Current Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Original Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Inventors: Arai, Yasuyuki, Akiba, Mai, Tachimura, Yuko
• Primary Examiner(s): PATEL, PARESH H
• Application Number:
  US11/044,982
• Publication Number:
  US 20050168235A1
• Time in Patent Office: 607 Days
• Field of Search: None
• US Class Current: 438/17
• CPC Class Codes: G01R 31/2886 Features relating to contacting the IC under test, e.g. probe heads; chucks G01R31/2865 takes precedence, test connections, e.g. test sockets, or probes per se, G01R1/04 or G01R1/06
• CPC Class Codes: G01R 31/2889 Interfaces, e.g. between probe and tester G01R31/31905 and G01R1/07364 take precedence
• CPC Class Codes: G01R 31/3025 Wireless interface with the DUT
• CPC Class Codes: G01R 31/303 of integrated circuits G01R31/305 - G01R31/315 take precedence
• CPC Class Codes: G06K 7/0095 Testing the sensing arrangement, e.g. testing if a magnetic card reader, bar code reader, RFID interrogator or smart card reader functions properly testing of electrical circuits G01R31/28

Abstract

The present invention provides an inspection system of ID chips that can supply a signal or power supply voltage to an ID chip without contact, and can increase throughput of an inspection process and an inspection method using the inspection system. The inspection system according to the present invention includes a plurality of inspection electrodes, a plurality of inspection antennas, a position control unit, a unit for applying voltage to each of the inspection antennas, and a unit for measuring potentials of the inspection electrodes. One feature of the inspection system is that a plurality of ID chips and the plurality of inspection electrodes are overlapped with a certain space therebetween, and the plurality of ID chips and the plurality of inspection antennas are overlapped with a certain space therebetween, and the plurality of ID chips are interposed between the plurality of inspection electrodes and the plurality of inspection antennas by the position control unit.

Claims

1. A method for manufacturing a semiconductor device comprising:

forming a plurality of TFTs over a substrate;

forming an antenna in an upper portion of the TFT;

forming an interlayer insulating film over the antenna;

forming a plurality of chips by forming a protective layer over the interlayer insulating film to cover the antenna;

supplying a signal or power supply voltage to each of the plurality of chips without contact with each antenna of the plurality of chips;

moving an inspection electrode with an arbitrary portion of the antenna or the whole antenna of each of the plurality of chips overlapped with the inspection electrode with a space therebetween;

conducting an inspection for grasping an operating state of each of the plurality of chips from a voltage of the inspection electrode and a position of the inspection electrode to the plurality of chips;

separating the substrate of the chips that have been inspected from the TFT and an antenna; and

attaching the TFT and the antenna that have been separated to a support medium.

2. The method for manufacturing a semiconductor device according to claim 1, wherein the substrate used for the chip is an insulator.

3. The method for manufacturing a semiconductor device according to claim 1, wherein the substrate is a glass substrate or a plastic substrate.

4. The method for manufacturing a semiconductor device according to claim 1, wherein the space between each antenna of the plurality of chips and the plurality of the inspection electrodes is controlled by flowing a fluid thereinto.

5. The method for manufacturing a semiconductor device according to claim 1, wherein an inspection method by which voltage applied to each antenna of the plurality of chips is calculated by a method of successive approximation, a Fourier transform method using a projection slice theorem, or a convolution theorem method to grasp an operating state of each of the plurality of chips is employed.

6. The method for manufacturing a semiconductor device according to claim 1, wherein the inspection electrode is rotated.

7. A method for manufacturing a semiconductor device comprising:

forming a plurality of TFTs over a substrate;

forming an antenna in an upper portion of the TFT;

forming an interlayer insulating film over the antenna;

forming a plurality of chips by forming a protective layer over the interlayer insulating film to cover the antenna;

supplying a signal or power supply voltage to each of the plurality of chips without contact by overlapping each antenna of the plurality of chips with an inspection electrode with a space therebetween;

moving the inspection electrode with an arbitrary portion of the antenna or the whole antenna of each of the plurality of chips overlapped with the inspection electrode with a space therebetween;

conducting an inspection for grasping an operating state of each of the plurality of chips from a voltage of the inspection electrode and a position of the inspection electrode to the plurality of chips;

separating the substrate of the chips that have been inspected from the TFT and an antenna; and

attaching the TFT and the antenna that have been separated to a support medium.

8. The method for manufacturing a semiconductor device according to claim 7, wherein the substrate used for the chip is an insulator.

9. The method for manufacturing a semiconductor device according to claim 7, wherein the substrate is a glass substrate or a plastic substrate.

10. The method for manufacturing a semiconductor device according to claim 7, wherein the space between each antenna of the plurality of chips and the plurality of the inspection electrodes is controlled by flowing a fluid thereinto.

11. The method for manufacturing a semiconductor device according to claim 7, wherein an inspection method by which voltage applied to each antenna of the plurality of chips is calculated by a method of successive approximation, a Fourier transform method using a projection slice theorem, or a convolution theorem method to grasp an operating state of each of the plurality of chips is employed.

12. The method for manufacturing a semiconductor device according to claim 7, wherein the inspection electrode is rotated.