Floating gate analog voltage level shift circuit and method for producing a voltage reference that operates on a low supply voltage

• US 7,113,017 B2
• Filed: 07/01/2004
• Issued: 09/26/2006
• Est. Priority Date: 07/01/2004
• Status: Expired due to Fees

• Current Assignee: Intersil Americas LLC (Renesas Electronics Corporation)
• Original Assignee: Intersil Americas LLC (Renesas Electronics Corporation)
• Inventors: Owen, William H.
• Primary Examiner(s): TON, MY TRANG
• Application Number:
  US10/884,234
• Publication Number:
  US 20060001470A1
• Time in Patent Office: 817 Days
• Field of Search: 365/185.01, 365/185.02, 365/185.23, 327/333
• US Class Current: 327/333
• CPC Class Codes: G11C 16/10 Programming or data input circuits
• CPC Class Codes: G11C 2207/2254 Calibration
• CPC Class Codes: G11C 7/062 Differential amplifiers of non-latching type, e.g. comparators, long-tailed pairs
• CPC Class Codes: G11C 7/067 Single-ended amplifiers
• CPC Class Codes: G11C 7/14 Dummy cell management; Sense reference voltage generators
• CPC Class Codes: H03K 5/08 by limiting; by thresholding; by slicing, i.e. combined limiting and thresholding H03K5/07 takes precedence; comparing one pulse with another H03K5/22; providing a determined threshold for switching H03K17/30
• CPC Class Codes: H03K 5/2481 with at least one differential stage

Abstract

A floating gate voltage level shift circuit is disclosed for generating a voltage reference which can operate on a low supply voltage Vcc by providing a circuit that enables the floating gate to be set accurately to a positive voltage during a SET operation and subsequently shifted down to a lower voltage for a READ operation. The floating gate voltage level shift circuit comprises a differential amplifier with two floating gates, a first floating gate and a second floating gate where the second floating gate is capacitively coupled to either a READ voltage or a Vshift voltage. The floating gate voltage level shift circuit operates in two primary modes, a SET operation and a READ operation. During the SET operation, the C1p capacitor of the second floating gate is connected to a Vshift voltage, rather than ground, while accurately setting the floating gate a positive voltage. The output of the differential amplifier typically swings a volt or more above and below the voltage of the second floating gate while settling to a desired voltage. During the READ operation, the C1p capacitor of the second floating gate is connected to ground, thereby causing the floating gate to shift down to a lower voltage which enables the voltage reference to work on low supply voltage.

Claims

1. A floating gate voltage level shift circuit, comprising:

a first floating gate for storing charge;

a second floating gate for storing charge;

a voltage shift capacitor having a first terminal coupled to the second floating gate and a second terminal; and

a differential amplifier, coupled between the first floating gate and the second floating gate, for causing the charge level on the first floating gate to be modified during a SET operation as a function of the voltage on the second floating gate;

wherein, during the SET operation, the second terminal of the voltage shift capacitor is coupled to a first predetermined voltage;

wherein, during a READ operation, the second terminal of the voltage shift capacitor is coupled to a second predetermined voltage.

2. The floating gate voltage level shift circuit of claim 1, wherein the second predetermined voltage comprises ground.

3. The floating gate voltage level shift circuit of claim 1, wherein the second predetermined voltage comprises a reference voltage.

4. The floating gate voltage level shift circuit of claim 1, further comprising a first and second tunnel device coupled to said first floating gate to operate in a dual conduction mode under the control of a voltage differential between a first tunnel electrode coupled to said first tunnel device and a second tunnel electrode coupled to said second tunnel device, for modifying the charge level on said first floating gate during said SET mode.

5. A floating gate voltage level shift circuit, comprising:

a first floating gate for storing charge;

a steering capacitor, coupled to the first floating gate, for controlling the charge level on the first floating gate as a function of an input set voltage that is coupled through the steering capacitor to the first floating gate during a SET operation;

a second floating gate for storing charge;

a voltage shift capacitor (C1p) having a first terminal coupled to the second floating gate and a second terminal coupled to a first predetermined voltage (Vfirst) during the SET operation and coupled to a second predetermined voltage (Vsecond) during a READ operation; and

wherein the second predetermined voltage comprises ground.

6. The floating gate voltage level shift circuit of claim 5, wherein, during the READ mode, the voltage shift capacitor is coupled to the second voltage potential such that the voltage on the second floating gate is capacitively shifted down to a lower voltage.

7. The floating gate voltage level shift circuit of claim 5, further comprising a first and second tunnel device coupled to said first floating gate to operate in a dual conduction mode under the control of a voltage differential between a first tunnel electrode coupled to said first tunnel device and a second tunnel electrode coupled to said second tunnel device, for modifying the charge level on said first floating gate during said SET mode.

8. The floating gate voltage level shift circuit of claim 5, further comprising a third capacitor (C1), connected between the second floating gate and ground such that the voltage shift of the second floating gate is proportional to (Vfirst−

Vsecond)*{C1p/(C1+C1p)}.

9. A floating gate voltage level shift circuit, comprising:

a first floating gate for storing charge;

a steering capacitor, coupled to the first floating gate, for controlling the charge level on the first floating gate as a function of an input set voltage that is coupled through the steering capacitor to the first floating gate during a SET operation;

a second floating gate for storing charge;

a voltage shift capacitor (C1p) having a first terminal coupled to the second floating gate and a second terminal coupled to a first predetermined voltage (Vfirst) during the SET operation and coupled to a second predetermined voltage (Vsecond) during a READ operation; and

a feedback circuit, coupled between the first floating gate and the second floating gate, for causing the charge level on the first floating gate to be modified during the SET operation until the voltage on the first floating gate is a predetermined function of the voltage on the second floating gate.

10. The floating gate voltage level circuit of claim 9, wherein the feedback circuit comprises:

a differential stage comprising a first, second, third and fourth transistor, each said transistor having a gate and a first and second terminal, wherein said first floating gate is the gate of said first transistor, said second floating gate is the gate of said second transistor, the first terminals of said first and second transistors are coupled together, the second terminals of said first and third transistors are coupled together and are further coupled to the gates of said third and fourth transistors, the second terminals of said second and fourth transistors are coupled together, and the first terminals of said third and fourth transistors are coupled together to a voltage source; and

a gain stage comprising a fifth transistor, having a gate and a first and second terminal, a gain stage current source, and a compensation capacitor, wherein the gate of said fifth transistor is coupled to the second terminals of said second and fourth transistors, the first terminal of said fifth transistor is coupled to the first terminals of said third and fourth transistors, said compensation capacitor is coupled between the gate and the second terminal of said fifth transistor, and the second terminal of said fifth transistor is coupled to said gain stage current source.

11. A method for operating a floating gate voltage level shift circuit having a first floating gate and a second floating gate, comprising:

coupling a first predetermined voltage to the second floating gate during a SET operation;

causing the voltage level on the first floating gate to be modified as a function of the second floating gate during the SET operation;

coupling a second predetermined voltage to the second floating gate during a READ operation such that the voltage level on the second floating gate is modified; and

wherein the second predetermined voltage comprises ground.

12. The method of claim 11, further comprising causing a first and second tunnel device coupled to said first floating gate to operate in a dual conduction mode under the control of a voltage differential between a first tunnel electrode coupled to said first tunnel device and a second tunnel electrode coupled to said second tunnel device, for modifying the charge level on said first floating gate during said SET mode.

13. The method of claim 11, further comprising coupling a Vset voltage to a steering capacitor, wherein the steering capacitor is coupled to said first floating gate.

14. A method for operating a floating gate voltage level shift circuit having a first floating gate and a second floating gate coupled to a differential amplifier, comprising:

coupling a first predetermined voltage to the second floating gate during a SET operation;

causing the voltage level on the first floating gate to be modified as a function of the second floating gate during the SET operation;

coupling a second predetermined voltage to the second floating gate during a READ operation such that the voltage level on the second floating gate is modified;

coupling a Vset voltage to a steering capacitor, wherein the steering capacitor is coupled to said first floating gate; and

measuring a Vdelta voltage which is added to the Vset voltage for one or more iterations of the SET operation to obtain a desired setting accuracy of an output voltage (Vout), wherein the value of Vdelta is equal to Vout(measured) minus Vout(desired).