Communication driver

• US 7,113,121 B1
• Filed: 07/12/2005
• Issued: 09/26/2006
• Est. Priority Date: 05/23/2000
• Status: Expired due to Fees

• Current Assignee: Marvell International Limited (Marvell Technology Group Limited)
• Original Assignee: Marvell International Limited (Marvell Technology Group Limited)
• Inventors: Sutardja, Sehat, Roo, Pierte
• Primary Examiner(s): Williams, Howard L.
• Application Number:
  US11/178,350
• Time in Patent Office: 441 Days
• Field of Search: 341/143, 341/144, 341/153, 375/259, 375/296, 375/297, 375/256
• US Class Current: 341/144
• CPC Class Codes: H03M 1/747 with equal currents which are switched by unary decoded digital signals

Abstract

An Ethernet controller includes a decoder, and T sets of transmit circuits. Each set of transmit circuits receives one of T decoded signals from the decoder, and includes a digital-to-analog converter (DAC) that provides a transmit output signal, and a replica circuit that provides a replica output signal. Each DAC includes N current sources arranged in parallel and differentially, and M delay elements. Each current source includes a control input. A sum of outputs of the N current sources forms each transmit output signal. An input of the first delay element and the control input of the first current source receive a decoded signal. An input of an mth delay element is in communication with an output of an m−1th delay element. The output of each delay element controls a corresponding control input of a current source. A sum of the transmit output signals forms an accumulated output signal.

Claims

1. A communication circuit, comprising:

a decoder configured to receive input signals and to provide T decoded signals;

a transmit section, wherein the transmit section comprises;

T sets of transmit circuits arranged in parallel,

wherein each of the T sets of transmit circuits is configured to receive a respective one of the T decoded signals,

wherein each of the T sets of transmit circuits comprises a digital-to-analog converter (DAC) and is configured to provide a transmit output signal,

wherein each DAC comprises;

N current sources arranged in parallel and in a differential configuration,

 

wherein each of the N current sources includes a respective control input, and

 

wherein the transmit output signal provided by the DAC comprises a sum of outputs of the N current sources; and

M delay elements,

 

wherein an input of a first one of the M delay elements and the control input of a first one of the N current sources are configured to receive the respective one of the T decoded signals,

 

wherein an mth one of the M delay elements includes an input in communication with an output of an m−

1th one of the M delay elements,

 

wherein the output of one of the M delay elements controls a corresponding control input of one of the N current sources,

wherein a sum of the transmit output signals from the T sets of transmit circuits forms an accumulated output signal,

wherein each of the T sets of transmit circuits comprises a replica circuit and is configured to provide a replica output signal,

wherein each replica circuit comprises;

N replica current sources arranged in parallel and in a differential configuration,

 

wherein each of the N replica current sources includes a respective control input,

 

wherein the control input of a first one of the N replica current sources is configured to receive the respective one of the T decoded signals,

 

wherein the output of the one of the M delay elements controls a corresponding control input of one of the N replica current sources,

 

wherein the replica output signal comprises a sum of outputs of the N replica current sources, and

wherein a sum of the replica output signals from the T sets of transmit circuits forms an accumulated replica output signal; and

a receive section,

wherein the receive section is configured to receive a composite signal and the accumulated replica output signal, and

wherein the receive section comprises;

a summer,

wherein the summer is configured to sum the composite signal and the accumulated replica output signal.

2. The communication circuit of claim 1, wherein the receive section comprises:

a compensation circuit.

3. The communication circuit of claim 2, wherein the summer is responsive to the compensation circuit.

4. The communication circuit of claim 2, wherein the summer is coupled to the compensation circuit.

5. The communication circuit of claim 2, wherein the compensation circuit is configured to perform baseline wander correction.

6. The communication circuit of claim 2, wherein the compensation circuit is configured to perform common mode correction.

7. The communication circuit of claim 2, wherein the summer is configured to sum an output of the compensation circuit and the composite signal and the accumulated replica output signal.

8. The communication circuit of claim 1, wherein T is equal to 16.

9. The communication circuit of claim 8, wherein N is equal to 10.

10. The communication circuit of claim 1, wherein at least one of the M delay elements comprises a delay lock loop.

11. A communication system, comprising:

means for decoding input signals to provide T decoded signals;

means for transmitting signals, wherein the signal transmitting means comprises;

T sets of means for generating a signal arranged in parallel,

wherein each of the T sets of signal generating means is configured to receive a respective one of the T decoded signals,

wherein each of the T sets of signal generating means comprises a means for converting digital signals to analog signals and is configured to provide a transmit output signal,

wherein each signal converting means comprises;

N means for generating current arranged in parallel and in a differential configuration,

 

wherein each of the N current generating means includes a respective control input, and

 

wherein the transmit output signal provided by the signal converting means comprises a sum of outputs of the N current generating means; and

M means for delaying signals,

 

wherein an input of a first one of the M signal delaying means and the control input of a first one of the N current generating means are configured to receive the respective one of the T decoded signals,

 

wherein an mth one of the M signal delaying means includes an input in communication with an output of an m−

1th one of the M signal delaying means,

 

wherein the output of one of the M signal delaying means controls a corresponding control input of one of the N current generating means,

wherein a sum of the transmit output signals from the T sets of signal generating means forms an accumulated output signal,

wherein each of the T sets of signal generating means comprises a means for generating a replica output signal,

wherein each replica output signal generating means comprises;

N means for generating a replica current arranged in parallel and in a differential configuration,

 

wherein each of the N replica current generating means includes a respective control input,

 

wherein the control input of a first one of the N replica current generating means is configured to receive the respective one of the T decoded signals, and

 

wherein the output of the one of the M signal delaying means controls a corresponding control input of one of the N replica current generating means,

 

wherein the replica output signal comprises a sum of outputs of the N replica current generating means, and

wherein a sum of the replica output signals from the T sets of signal generating means forms an accumulated replica output signal; and

means for receiving signals,

wherein the signal receiving means is configured to receive a composite signal and the accumulated replica output signal, and

wherein the signal receiving means comprises;

means for summing,

wherein the summing means is responsive to the composite signal and the accumulated replica output signal.

12. The communication system of claim 11, wherein the signal receiving means comprises:

compensation means for outputting a compensation signal.

13. The communication system of claim 12, wherein the summing means is responsive to the compensation means.

14. The communication system of claim 12, wherein the summing means is coupled to the compensation means.

15. The communication system of claim 12, wherein the compensation means is configured to perform baseline wander correction.

16. The communication system of claim 12, wherein the compensation means is configured to perform common mode correction.

17. The communication system of claim 12, wherein the summing means is configured to sum the compensation signal and the composite signal and the accumulated replica output signal.

18. The communication system of claim 11, wherein T is equal to 16.

19. The communication system of claim 18, wherein N is equal to 10.

20. The communication system of claim 11, wherein at least one of the M signal delaying means comprises a delay lock loop means.

21. A method of communicating signals, comprising the steps of:

a.) decoding T input signals to provide T decoded signals;

b.) transmitting signals, wherein step (b) comprises the steps of;

b1.) differentially providing T transmit output signals in accordance with the T decoded signals,

wherein for each transmit output signal, step (b1) comprises the steps of;

1.) supplying N sources of current;

2.) controlling the supply of current from each of the N sources of current;

3.) delaying current from M of the N sources of current,

 

wherein an input of a first one of the M delaying steps and a control input of a first one of the N sources of current receive a respective one of the T decoded signals,

 

wherein an input of the mth one of the M delaying steps receives a signal from an m−

1th one of the M delaying steps, and

 

wherein an output of one of the M delaying steps controls a corresponding one of the N sources of current; and

4.) summing the delayed currents;

b2.) differentially providing T replica output signals in accordance with the T decoded signals,

wherein for each replica output signal, step (b2) comprises the steps of;

1.) supplying N sources of replica current;

2.) controlling the supply of current from each of the N sources of replica current,

 

wherein a control input of a first one of the N sources of replica current receives the respective one of the T decoded signals,

 

wherein the output of the one of the M delaying steps controls a corresponding one of the N sources of replica current, and

3.) summing outputs of the N sources of replica current;

b3.) summing the T transmit output signals to generate an accumulated output signal;

b4.) summing the T replica output signals to generate an accumulated replica output signal;

c.) receiving a composite signal and the accumulated replica output signal; and

d.) summing the composite signal and the accumulated replica output signal.

22. The method of claim 21, wherein step (c) comprises the step of:

c1.) receiving a compensation signal.

23. The method of claim 22, wherein the compensation signal is configured for baseline wander correction.

24. The method of claim 22, wherein the compensation signal is configured for common mode correction.

25. The method of claim 22, wherein step (d) comprises the step of:

d1.) summing the compensation signal and the composite signal and the accumulated replica output signal.

26. The method of claim 21, wherein T is equal to 16.

27. The method of claim 26, wherein N is equal to 10.