Controller area network transceiver having capacitive balancing circuit for improved receiver common-mode rejection

• US 7,113,759 B2
• Filed: 08/28/2002
• Issued: 09/26/2006
• Est. Priority Date: 08/28/2002
• Status: Active Grant

• Current Assignee: Texas Instruments, Inc.
• Original Assignee: Texas Instruments, Inc.
• Inventors: Jordanger, Ricky D., Antonsen, Anton M.
• Primary Examiner(s): Vo, Nguyen T.
• Assistant Examiner(s): Le, Nhan T.
• Application Number:
  US10/229,516
• Publication Number:
  US 20040043739A1
• Time in Patent Office: 1,490 Days
• Field of Search: 455/73, 455/80, 455/107, 455/280, 455/281, 455/127.1, 455/127.5, 455/131, 333/17.3, 333/124
• US Class Current: 455/281
• CPC Class Codes: H04B 3/30 Reducing interference caused by unbalanced currents in a normally balanced line

Abstract

A controller area network transceiver and a transmission method for a controller area network provides improved symmetry between its differential output signal CANH and CANL such that capacitive imbalance is minimized. The transceiver disclosed herein includes a driver including a non-inverted output that couples to the first output terminal CANH and a inverted output that couples to the second output terminal CANL. A receiver comparator includes a non-inverted input coupled to the first output terminal CANH and a inverted input coupled to the second output terminal CANL. A first and second impedance matching circuit portions capacitively balance the first and second output terminals such that efficient common-mode rejection is enabled by setting the RC time constants formed by each impedance matching circuit and external resistances to be substantially equivalent. This transceiver provides a high performance, simple, and cost effective design which eliminates capacitive imbalance while decreasing required die area.

Claims

1. A controller area network transceiver including a power supply rail, a first and a second output terminal, comprising:

a driver, having an input, a non-inverted and an inverted output, to generate a first and second output signal at the respective non-inverted and inverted outputs, the non-inverted output coupled to the first output terminal, the inverted output coupled to the second output terminal;

a receiver comparator having a non-inverted and an inverted input and an output, the non-inverted input coupled to the first output terminal, the inverted input coupled to the second output terminal;

a first impedance matching circuit portion coupled between the non-inverted output of the driver and the non-inverted input of the receiver comparator to receive the first output signal and to provide a first capacitance at the first output terminal; and

a second impedance matching circuit portion coupled between the inverted output of the driver and the inverted input of the receiver comparator to receive the second output signal and to provide a second capacitance at the second output terminal, the first and second impedance matching circuit portions capacitively balance the first and second output terminals such that the first capacitance substantially equals the second capacitance to enable receiver common-mode rejection,

wherein the second impedance matching circuit portion comprises;

a first transistor having a bulk, a gate, a drain and a source, the gate coupled to the power supply rail, a drain coupled to receive the second output signal;

a first diode coupled between the power supply rail and the bulk of the first transistor;

a capacitor coupled between the source of the first transistor and ground;

a second diode coupled to receive the second output signal; and

a second transistor having a bulk, a gate, a drain and a source, the gate coupled to receive a pre-drive signal, the drain coupled to the second diode, the source and bulk coupled to ground.

2. A controller area network transceiver as recited in claim 1, wherein the first diode is a Schottky diode.

3. A controller area network transceiver as recited in claim 1, wherein the second diode is a Schottky diode.

4. A controller area network transceiver including a power supply rail, a first and a second output terminal, comprising:

a driver, having an input, a non-inverted and an inverted output, to generate a first and second output signal at the respective non-inverted and inverted outputs, the non-inverted output coupled to the first output terminal, the inverted output coupled to the second output terminal;

a receiver comparator having a non-inverted and an inverted input and an output, the non-inverted input coupled to the first output terminal, the inverted input coupled to the second output terminal;

a first impedance matching circuit portion coupled between the non-inverted output of the driver and the non-inverted input of the receiver comparator to receive the first output signal, the first impedance matching circuit portion configured such that when receiver common-mode rejection testing occurs, the first impedance matching circuit portion couples to a first external resistor to form a first RC time constant; and

a second impedance matching circuit portion coupled between the inverted output of the driver and the inverted input of the receiver comparator to receive the second output signal, the second impedance matching circuit portion configured such that when receiver common-mode rejection testing occurs, the second impedance matching circuit portion couples to a second external resistor to form a second RC time constant, the first and second impedance matching circuit portions capacitively balance the first and second output terminals such that the first RC time constant substantially equals the second RC time constant to enable receiver common-mode rejection,

wherein the second impedance matching circuit portion comprises;

a first transistor having a bulk, a gate, a drain and a source, the gate coupled to the power supply rail, a drain coupled to receive the second output signal;

a first diode coupled between the power supply rail and the bulk of the first transistor;

a capacitor coupled between the source of the first transistor and ground;

a second diode coupled to receive the second output signal; and

a second transistor having a bulk, a gate, a drain and a source, the gate coupled to receive a pre-drive signal, the drain coupled to the second diode, the source and bulk coupled to ground.

5. A controller area network transceiver as recited in claim 4, wherein the first diode is a Schottky diode.

6. A controller area network transceiver as recited in claim 4, wherein the second diode is a Schottky diode.