Computing system with operational low power states

• US 7,114,090 B2
• Filed: 02/14/2003
• Issued: 09/26/2006
• Est. Priority Date: 02/14/2003
• Status: Expired due to Fees

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Fleming, Kristoffer D., Gupta, Vivek, Gadamsetty, Uma M., Kardach, James P., Forand, Richard A., Belmont, Brian V., Huckins, Jeffrey L., Kumar, Muthu K., Jackson, Riley W., Danneels, Gunner
• Primary Examiner(s): Elamin, A.
• Assistant Examiner(s): Patel, Nitin C.
• Application Number:
  US10/367,240
• Publication Number:
  US 20040163005A1
• Time in Patent Office: 1,320 Days
• Field of Search: 713/300, 713/320, 713/322, 713/323, 713/324
• US Class Current: 713/323
• CPC Class Codes: G06F 1/3203 Power management, i.e. event-based initiation of a power-saving mode
• CPC Class Codes: G06F 1/3287 by switching off individual functional units in the computer system
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management
• CPC Class Codes: Y02D 30/00 Reducing energy consumption in communication networks
• CPC Class Codes: Y02D 30/50 in wire-line communication networks, e.g. low power modes or reduced link rate

Abstract

A method is described that involves operating a computing system within a normal on state and transitioning from the normal on state to a main CPU/OS based state. In the main CPU/OS based state one or more components of the computing system are inactivated so as to cause the computing system to consume less power in the main CPU/OS based state than in the normal on state. The computing system is able to execute software application routines on a main CPU and a main OS of the computing system while in the main CPU/OS based state.

Claims

1. A method, comprising:

a) operating a computing system within a normal on state; and

b) transitioning from said normal on state to a main Central Processing Unit/Operating System (“

CPU/OS”

) based state in which one or more components of said computing system other than a main CPU of said computing system are inactivated so as to cause said computing system to consume less power in said main CPU/OS based state than in said normal on state, said one or more components including a graphics controller, said computing system able to execute one or more application software routines within said main CPU/OS based state, wherein said transitioning from said normal on state to said main CPU/OS based state further comprises stripping one or more components of said computing system of their ability to control their own power consumption.

2. The method of claim 1 wherein said transitioning from said normal on state to said main CPU/OS based state further comprises suspending one or more application software programs that are executed within said normal on state.

3. The method of claim 2 wherein said one or more inactivated components at least include a main display.

4. The method of claim 1 wherein said computing system is an Advanced Configuration and Power Interface (“

ACPI”

) compliant system and said one or more components are forced to operate in a D3 state.

5. The method of claim 1 wherein said transitioning from said normal on state to said main CPU/OS based state further comprises forcing said main CPU to operate in a lower performance/lower power operational state.

6. The method of claim 5 wherein said lower performance/lower power operational state is effected by lowering a main CPU voltage.

7. The method of claim 5 wherein said lower performance/lower power operational state is effected by lowering a main CPU clock frequency.

8. The method of claim 5 wherein said lower performance/lower power operational state is effected by lowering a main CPU voltage and a main CPU clock frequency.

9. The method of claim 5 wherein said lower performance/lower power operational state is a P₄ state.

10. The method of claim 1 wherein said main CPU further comprises multiple CPUs and wherein said transitioning from said normal on state to said main CPU/OS based state further comprises inactivating all but one of said multiple CPUs.

11. The method of claim 1 wherein said one or more components that are inactivated within said main CPU/OS based state include a display.

12. The method of claim 1 further comprising:

c) transitioning from said main CPU/OS based state to a non main CPU/OS based state in which additional components of said computing system are inactivated so as to cause said computing system to consume less power in said non main CPU/OS based state than in said main CPU/OS based state, said main CPU and said main OS unable to execute application software routines within said non main CPU/OS based state, said computing system able to perform one or more tasks for a user within said non main CPU/OS based state.

13. The method of claim 12 wherein said transitioning from said main CPU/OS based state to said non main CPU/OS based state further comprises placing said main CPU and said main OS in a sleep state so that said additional components include at least said main CPU and said main OS.

14. The method of claim 13 wherein said placing said main CPU and said main OS in a sleep state further comprises activating at least one bit that causes wake up/sleep logic embedded within said computing system to establish a power supply voltage scheme that at least helps to cause said computing system to consume less power in said non main CPU/OS based state than in said main CPU/OS based state.

15. The method of claim 14 wherein said bit is an SLP_EN bit and said computing system is an ACPI compliant system.

16. The method of claim 14 wherein said bit is not an SLP_EN bit and said computing system is an ACPI compliant system.

17. The method of claim 14 wherein said placing said main CPU and said main OS in a sleep state further comprises recording that said computing system is entering said non main CPU/OS based state so that a subsequent transitioning from said non main CPU/OS based state back to said main CPU/OS based state can be recognized as said main CPU and main OS awake from said sleep state.

18. The method of claim 17 wherein said recording further comprises establishing values for a group of SLP_TYP bits and wherein said computing system is an ACPI compliant system.

19. The method of claim 12 wherein said transitioning from said main CPU/OS based state to said non main CPU/OS based state further comprises inactivating said computing system'"'"'s main system memory.

20. The method of claim 12 wherein said transitioning from said main CPU/OS based state to said non main CPU/OS based state further comprises inactivating one or more communication interfaces to an I/O controller within said computing system.

21. The method of claim 20 wherein said one or more communication interfaces further comprise a Universal Serial Bus.

22. The method of claim 20 wherein said one or more communication interfaces further comprise a storage device communication interface.

23. The method of claim 20 wherein said one or more communication interfaces further comprise a serial interface and/or a serial port interface.

24. A computing system, comprising:

a normal on operating state in which said computing system'"'"'s main CPU is allowed to alter its power consumption states as it executes one or more application software programs; and

,

a main CPU/OS based low power operating state in which;

1) said computing system'"'"'s main CPU is forced to execute one or more application software programs within a lowest power consumption state at which application software programs can be executed; and

,

2) one or more components of said computing system that are allowed to regulate their own power consumption during said normal on state are not allowed to regulate their own power consumption during said main CPU/OS based low power state.

25. The computing system of claim 24 wherein at least one of said one or more application program software programs that are executed during said normal on operating state are suspended while said main CPU/OS based low power state is maintained.

26. The computing system of claim 24 wherein said computing system is an ACPI compliant system and said components are forced to operate within a D3 state while said main CPU/OS based low power state is maintained.

27. The computing system of claim 24 wherein said main CPU further comprises multiple CPUs and wherein said main CPU/OS based low power state is further characterized in that only one of said CPUs is allowed to operate one or more application software programs.

28. The computing system of claim 24 wherein, while said CPU is within said lowest power consumption state, said CPU is operated with a lowest voltage at which said CPU can execute application software programs.

29. The computing system of claim 28 wherein, while said CPU is within said lowest power consumption state, said CPU is operated with a lower clock frequency as compared to said normal on state.

30. The computing system of claim 29 wherein said lowest power consumption state is a P₄ state.

31. The computing system of claim 24 wherein said one or more components further comprise said computing system'"'"'s main display.

32. The computing system of claim 24 wherein said one or more components further comprise said computing system'"'"'s graphics controller.

33. The computing system of claim 24 wherein said one or more components further comprise said computing system'"'"'s disk drive.

34. The computing system of claim 24 wherein said computing system further comprises:

a non main CPU/OS based operating state in which;

1) said main CPU and a main OS that is executed upon said main CPU are put to sleep;

2) one or more I/O units that emanate from an I/O controller are inactivated; and

,

3) a controller that is active within said normal on operating state and said main CPU/OS based low power operating state remains active within said non main CPU/OS based operating state.

35. A machine readable medium having stored thereon instructions which, when executed by a CPU, cause said CPU to perform a method, said method comprising:

a) operating within a normal on state by supporting the execution of one or more application software programs while allowing each one of one or more components of a computing system that said CPU is a part of to control its own power consumption; and

,

b) operating within a low power state by supporting the execution of at least one of said application software programs while not allowing each one of said one or more components to control its own power consumption and while each one of said one or more components are forced to operate within a low power consumption state.

36. The machine readable medium of claim 35 where said method further comprises, as part of a transition process from said normal on state to said low power state, marking that said low power state is active.

37. The machine readable medium of claim 35 wherein said method further comprises, as part of a transition process from said normal on state to said low power state, suspending at least one of said application software programs other than said at least one application software program executed during said low power state.

38. The machine readable medium of claim 37 wherein said method further comprise, as part of said suspending, storing the context of those of said application software programs that are suspended.

39. The machine readable medium of claim 35 wherein said method further comprises, as part of a transition process from said normal on state to said low power state, forcing said CPU into a lowest power consumption state at which application software programs can be executed.

40. The machine readable medium of claim 39 wherein said lowest power consumption state at which application software programs can be executed further comprises a P₄ state.

41. The machine readable medium of claim 39 wherein said forcing further comprises lowering a CPU clock frequency.

42. The machine readable medium of claim 39 wherein said forcing further comprises lowering a CPU voltage.

43. The machine readable medium of claim 35 wherein said method further comprises, as part of a transition from said low power state into a second low power state in which said CPU does not execute application software application programs, setting at least one bit to cause a power supply scheme that supports said second state to be established.

44. The machine readable medium of claim 43 wherein said method further comprises, as part of said transition from said low power state to said second tow power state, storing context of an operating system that is executed upon said CPU.

45. The machine readable medium of claim 43 wherein said computing system may perform a task for a user while said computing system is within said second low power state.

46. The machine readable medium of claim 45 wherein said computing system is an ACPI compliant system and said at least one bit is an SLP_EN bit.

47. The machine readable medium of claim 45 wherein said computing system is an ACPI compliant system and said at least one bit is not an SLP_EN bit.

48. The machine readable medium of claim 47 wherein said method further comprises, as part of a transition process from said second low power state back to said low power state, identifying an event that occurred within said second low power state so as to cause said transition back to said low power state.

49. The machine readable medium of claim 48 wherein said method further comprises, as part of said transition from said second low power state back to said low power state, restoring context that was stored as part of said transition from said low power state to said second low power state.

50. An apparatus, comprising:

circuitry that remains powered while a computing system'"'"'s main CPU and main OS are sleeping as said computing system operates within a non main CPU/OS based operating state, said circuitry further comprising;

a) a first input to receive a first indication, said first indication part of a first state transition process of said computing system to said non main CPU/OS based operating state;

b) a second input to receive a second indication, said second indication part of a second state transition process of said computing system from said non main CPU/OS based operating state; and

,

c) wake up/sleep logic that is responsive to said first indication and said second indication, said wake up /sleep logic to;

(i) establish a first power scheme in response to said first indication, said first power scheme to power said computing system while said computing system is within said non main CPU based operating state and

(ii) establish a second power scheme in response to said second indication, where, said second power scheme allows said main CPU and said main OS to wake up.

51. The apparatus of claim 50 further comprising a third input to receive a third indication, said third indication part of a third state transition process of said computing system to a traditional ACPI sleep state.

52. The apparatus of claim 51 wherein and said third input comprises a set of SLP_TYP bits.

53. The apparatus of claim 51 wherein said circuitry is integrated within a memory and I/O control function of said computing system.

54. The apparatus of claim 53 wherein said circuitry is integrated into a memory controller semiconductor chip.

55. The apparatus of claim 53 wherein said circuitry is integrated into an Input/Output (“

I/O”

), controller semiconductor chip.

56. The apparatus of claim 50 wherein said first input can also receive a third indication, said third indication part of a third state transition process of said computing system to a traditional ACPI sleep state.

57. The apparatus of claim 56 wherein said third input comprises a set of SLP_TYP bits.

58. The apparatus of claim 56 wherein said third input comprise a SLP_EN bit.

59. The apparatus of claim 56 wherein said circuitry is integrated within a memory and I/O control function of said computing system.

60. The apparatus of claim 59 wherein said circuitry is integrated into a memory controller semiconductor chip.

61. The apparatus of claim 59 wherein said circuitry is integrated into an I/O controller semiconductor chip.