Semiconductor test system and method for effectively testing a semiconductor device having many pins

• US 7,114,108 B2
• Filed: 10/30/2001
• Issued: 09/26/2006
• Est. Priority Date: 01/26/2001
• Status: Expired due to Term

• Current Assignee: Samsung Electronics Co. Ltd. (Samsung Group)
• Original Assignee: Samsung Electronics Co. Ltd. (Samsung Group)
• Inventors: An, Sang-Bae, Park, Heon-Deok, Jeon, Jae-Kuk
• Primary Examiner(s): Lamarre, Guy
• Assistant Examiner(s): Kerveros, James C.
• Application Number:
  US10/003,180
• Publication Number:
  US 20020104049A1
• Time in Patent Office: 1,792 Days
• Field of Search: 714/718, 714/719
• US Class Current: 714/719
• CPC Class Codes: G11C 29/48 Arrangements in static stores specially adapted for testing by means external to the store, e.g. using direct memory access [DMA] or using auxiliary access paths

Abstract

A semiconductor device having many pins is tested using a test system having fewer pins. The test system includes a pin electronics (PE) card and a pattern memory. The PE card preferably includes a plurality of comparator and driver units to drive predetermined input signal pattern to be applied to an input pin of the semiconductor device and to compare data output from an output pin of the semiconductor device with a predetermined output signal pattern. Some or all of the pins of the semiconductor device may be divided into pin groups having K number of pins. The PE card also preferably includes a plurality of control units for electrically connecting each of the comparator and driver units to a selected pin in a selected pin group in response to a control signal.

Claims

1. A semiconductor device test system comprising:

a plurality of comparator and driver units, each comparator and driver unit comprising a driver configured to drive an input signal pattern to be applied to two or more input pins of the semiconductor device and a comparator configured to compare data output from two or more output pins of the semiconductor device with a predetermined output signal pattern;

a plurality of control units, each control unit configured to electrically connect a corresponding comparator and driver unit to a pin of the semiconductor device in response to a control signal, wherein pins of the semiconductor device are divided into pin groups, each pin group having K number of pins, where K is an integer greater than 1; and

a pattern memory for storing the input signal patterns and the output signal patterns, the pattern memory including;

an input pattern memory for storing input signal patterns; and

an output pattern memory for storing output signal patterns, wherein the output pattern memory stores K output signal patterns retrievable from an external device.

2. The semiconductor device test system according to claim 1, wherein each control unit is a multiplexer having K number of inputs.

3. The semiconductor device test system according to claim 1, wherein each control unit is configured to receive the control signal via a data bus.

4. The semiconductor device test system according to claim 1, wherein the external device is a hard disk drive.

5. The semiconductor device test system according to claim 1, wherein the pins of each pin group are input pins, and wherein the input pattern memory stores input signal patterns from an external device according to a state of the control signal.

6. The semiconductor device test system according to claim 1, wherein the pins of each pin group include input pins and/or output pins, and wherein the input pattern memory stores the input signal patterns from an external device according to a state of the control signal.

7. The semiconductor device test system according to claim 1, wherein the pins of each pin group are output pins, and wherein the predicted output signal patterns are stored in a buffer memory and loaded into the output pattern memory as occasion demands.

8. A method of testing a semiconductor device, the method comprising:

selecting pins from among a plurality of pins of the semiconductor device;

dividing the selected pins into a plurality of pin groups, each pin group comprising a desired plural number of pins;

generating a control signal;

electrically connecting a comparator and driver unit to a single pin in a corresponding one of the pin groups of the semiconductor device according to the control signal;

applying input signal patterns from an input pattern memory to the single pin; and

comparing data output from output pins of the semiconductor device via the single pin with output signal patterns output from an output pattern memory that stores the desired plural number of output signal patterns retrievable from an external device.

9. The method according to claim 8, wherein the selected pins are input pins of the semiconductor device, and wherein the input signal patterns are stored in the input pattern memory according to a state of the control signal.

10. The method according to claim 8, wherein the selected pins are output pins of the semiconductor device, and wherein the output signal patterns are stored in the output pattern memory according to a state of the control signal.

11. The method according to claim 8, wherein all of the pins of the semiconductor device are selected and divided into pin groups, wherein the input signal patterns are output from the external storage device and stored in the input pattern memory according to a state of the control signal, and wherein the output signal patterns are output from the external storage device and stored in the output pattern memory according to the state of the control signal.

12. A method of testing a semiconductor device having many pins using a test system having fewer pins, said method comprising:

selectively connecting a pin of the test system to a pin of the semiconductor device based on a control signal;

applying an input signal pattern to the pin of the semiconductor device;

comparing data output from the semiconductor device with a predetermined output signal pattern that is stored in a hard disk; and

storing the predetermined output signal pattern responsive to the control signal, wherein the hard disk outputs the predetermined output signal pattern to an output pattern memory that stores the predetermined output signal pattern, and wherein the output pattern memory is connected between the hard disk and the semiconductor device.

13. The method according to claim 12, wherein the pin of the test system comprises a comparator and driver unit, said comparator and driver unit comprising a comparator configured to compare an output pattern from an output pin of the semiconductor device with a predetermined output pattern and a driver configured to drive an input pattern for an input pin of the semiconductor device, and wherein the comparator and driver unit is selectively connected to the pin of the semiconductor device based on the control signal.

14. The method according to claim 12, wherein pins of the semiconductor device are divided into a plurality of pin groups, each pin group comprising a plurality of pins.

15. The method according to claim 14, wherein the pin of the test system is selectively connected to one of the pins in a corresponding pin group via a control unit based on the control signal.

16. The method according to claim 14, wherein the pin of the test system comprises a comparator and driver unit and a control unit and wherein the control unit selectively connects one of the pins from a corresponding pin group to the comparator and driver unit based on the control signal.