Semiconductor test system and method for effectively testing a semiconductor device having many pins
First Claim
1. A semiconductor device test system comprising:
- a plurality of comparator and driver units, each comparator and driver unit comprising a driver configured to drive an input signal pattern to be applied to two or more input pins of the semiconductor device and a comparator configured to compare data output from two or more output pins of the semiconductor device with a predetermined output signal pattern;
a plurality of control units, each control unit configured to electrically connect a corresponding comparator and driver unit to a pin of the semiconductor device in response to a control signal, wherein pins of the semiconductor device are divided into pin groups, each pin group having K number of pins, where K is an integer greater than 1; and
a pattern memory for storing the input signal patterns and the output signal patterns, the pattern memory including;
an input pattern memory for storing input signal patterns; and
an output pattern memory for storing output signal patterns, wherein the output pattern memory stores K output signal patterns retrievable from an external device.
1 Assignment
0 Petitions
Accused Products
Abstract
A semiconductor device having many pins is tested using a test system having fewer pins. The test system includes a pin electronics (PE) card and a pattern memory. The PE card preferably includes a plurality of comparator and driver units to drive predetermined input signal pattern to be applied to an input pin of the semiconductor device and to compare data output from an output pin of the semiconductor device with a predetermined output signal pattern. Some or all of the pins of the semiconductor device may be divided into pin groups having K number of pins. The PE card also preferably includes a plurality of control units for electrically connecting each of the comparator and driver units to a selected pin in a selected pin group in response to a control signal.
-
Citations
16 Claims
-
1. A semiconductor device test system comprising:
-
a plurality of comparator and driver units, each comparator and driver unit comprising a driver configured to drive an input signal pattern to be applied to two or more input pins of the semiconductor device and a comparator configured to compare data output from two or more output pins of the semiconductor device with a predetermined output signal pattern; a plurality of control units, each control unit configured to electrically connect a corresponding comparator and driver unit to a pin of the semiconductor device in response to a control signal, wherein pins of the semiconductor device are divided into pin groups, each pin group having K number of pins, where K is an integer greater than 1; and a pattern memory for storing the input signal patterns and the output signal patterns, the pattern memory including; an input pattern memory for storing input signal patterns; and an output pattern memory for storing output signal patterns, wherein the output pattern memory stores K output signal patterns retrievable from an external device. - View Dependent Claims (2, 3, 4, 5, 6, 7)
-
-
8. A method of testing a semiconductor device, the method comprising:
-
selecting pins from among a plurality of pins of the semiconductor device; dividing the selected pins into a plurality of pin groups, each pin group comprising a desired plural number of pins; generating a control signal; electrically connecting a comparator and driver unit to a single pin in a corresponding one of the pin groups of the semiconductor device according to the control signal; applying input signal patterns from an input pattern memory to the single pin; and comparing data output from output pins of the semiconductor device via the single pin with output signal patterns output from an output pattern memory that stores the desired plural number of output signal patterns retrievable from an external device. - View Dependent Claims (9, 10, 11)
-
-
12. A method of testing a semiconductor device having many pins using a test system having fewer pins, said method comprising:
-
selectively connecting a pin of the test system to a pin of the semiconductor device based on a control signal; applying an input signal pattern to the pin of the semiconductor device; comparing data output from the semiconductor device with a predetermined output signal pattern that is stored in a hard disk; and storing the predetermined output signal pattern responsive to the control signal, wherein the hard disk outputs the predetermined output signal pattern to an output pattern memory that stores the predetermined output signal pattern, and wherein the output pattern memory is connected between the hard disk and the semiconductor device. - View Dependent Claims (13, 14, 15, 16)
-
Specification