System and method for lithography simulation

• US 7,114,145 B2
• Filed: 11/16/2004
• Issued: 09/26/2006
• Est. Priority Date: 10/07/2003
• Status: Active Grant

• Current Assignee: ASML Netherlands BV (ASML Holding NV)
• Original Assignee: Brion Technologies Incorporated (ASML Holding NV)
• Inventors: Ye, Jun, Chen, Luoqi, Chen, Xun, Lu, Yen-Wen, Cao, Yu
• Primary Examiner(s): Kik, Phallaka
• Application Number:
  US10/989,972
• Publication Number:
  US 20050091633A1
• Time in Patent Office: 679 Days
• Field of Search: 716/21, 430/5, 378/35, 700/97, 700/120, 700/121, 250/492.22
• US Class Current: 716/52
• CPC Class Codes: G03F 1/00 Originals for photomechanical production of textured or patterned surfaces, e.g., masks, photo-masks, reticles; Mask blanks or pellicles therefor; Containers specially adapted therefor; Preparation thereof
• CPC Class Codes: G03F 7/004 Photosensitive materials G03F7/12, G03F7/14 take precedence
• CPC Class Codes: G03F 7/705 Modelling or simulating from physical phenomena up to complete wafer processes or whole workflow in wafer productions
• CPC Class Codes: G03F 7/70666 Aerial image, i.e. measuring the image of the patterned exposure light at the image plane of the projection system
• CPC Class Codes: G06F 2119/18 Manufacturability analysis or optimisation for manufacturability
• CPC Class Codes: G06F 30/20 Design optimisation, verification or simulation optimisation, verification or simulation of circuit designs G06F30/30
• CPC Class Codes: G06F 30/333 Design for testability [DFT], e.g. scan chain or built-in self-test [BIST]
• CPC Class Codes: G06F 30/398 Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM] optical proximity correction [OPC] design processes G03F1/36
• CPC Class Codes: G06T 2207/30148 Semiconductor; IC; Wafer
• CPC Class Codes: G06T 7/0004 Industrial image inspection
• CPC Class Codes: G16Z 99/00 Subject matter not provided for in other main groups of this subclass
• CPC Class Codes: G21K 5/00 Irradiation devices discharge tubes for irradiating H01J37/00

Abstract

There are many inventions described and illustrated herein. In one aspect, the present invention is directed to a technique of, and system for simulating, verifying, inspecting, characterizing, determining and/or evaluating the lithographic designs, techniques and/or systems, and/or individual functions performed thereby or components used therein. In one embodiment, the present invention is a system and method that accelerates lithography simulation, inspection, characterization and/or evaluation of the optical characteristics and/or properties, as well as the effects and/or interactions of lithographic systems and processing techniques. In this regard, in one embodiment, the present invention employs a lithography simulation system architecture, including application-specific hardware accelerators, and a processing technique to accelerate and facilitate verification, characterization and/or inspection of a mask design, for example, RET design, including detailed simulation and characterization of the entire lithography process to verify that the design achieves and/or provides the desired results on final wafer pattern. The system includes: (1) general purpose-type computing device(s) to perform the case-based logic having branches and inter-dependency in the data handling and (2) accelerator subsystems to perform a majority of the computation intensive tasks.

Claims

1. A method for evaluating a response of a lithographic design on wafer to a change in at least one process parameter of a photolithographic process, wherein the photolithographic process uses photolithographic equipment, the method comprising:

generating a pixel-based bitmap representation of a lithographic design, wherein the pixel-based bitmap includes pixel data, and wherein each pixel datum represents a pixel having a predetermined pixel size;

generating a first simulated image of the lithographic design on wafer using (1) the pixel-based bitmap representation of the lithographic design and (2) a first relationship representing an imaging path of projection and illumination optics of the photolithographic process;

generating a second simulated image of the lithographic design on wafer using (1) the pixel-based bitmap representation of the lithographic design and (2) a second relationship representing an imaging path of projection and illumination optics of the photolithographic process;

wherein a difference between (i) the first relationship representing the imaging path of the projection and illumination optics of the photolithographic process and (ii) the second relationship representing the imaging path of the projection and illumination optics of the photolithographic process includes the change in the at least one process parameter of the photolithographic process; and

determining the response of the lithographic design on wafer to the change in the at least one process parameter of the photolithographic process using the first simulated image and the second simulated image.

2. The method of claim 1, wherein lithographic design includes a plurality of polygons arranged in a predetermined configuration.

3. The method of claim 1, wherein the change in the at least one process parameter of the photolithographic process is a change in focus, illumination dose, numerical aperture or illumination aperture of the photolithographic equipment.

4. The method of claim 1, wherein lithographic design is a localized region of an integrated circuit design.

5. The method of claim 1, further including determining a configuration of settings of the photolithographic equipment using the determination of the response of the lithographic design on wafer to the change in the at least one process parameter of the photolithographic process.

6. The method of claim 5, wherein the configuration of settings of the photolithographic equipment includes at least one of the focus, illumination dose, numerical aperture or illumination aperture of the photolithographic equipment.

7. The method of claim 1, further including determining lithography settings using the determination of the response of the lithographic design on wafer to the change in the at least one process parameter of the photolithographic process.

8. The method of claim 7, wherein the lithographic settings include at least one of the photolithographic settings of the photolithographic equipment, resist processing parameters or resist stack design.

9. The method of claim 1, wherein the pixel-based bitmap is a gray-level image which is representative of a plurality of polygons.

10. The method of claim 1, wherein the predetermined pixel size provides a sampling frequency that is greater than a Nyquist frequency in an image of the lithographic design on wafer.

11. The method of claim 1, wherein the predetermined pixel size is determined using a numerical aperture and wavelength of projection optics of the photolithographic equipment.

12. The method of claim 1, wherein the lithographic design includes resolution enhancement technology.

13. The method of claim 1, wherein the first and second relationships representing the imaging path of the projection and illumination optics are coefficient matrices representing the imaging path of the projection and illumination optics of the photolithographic equipment.

14. The method of claim 13, wherein each coefficient matrix is representative of one or more of a focus, dose, numerical aperture, illumination aperture, and aberration of the photolithographic equipment.

15. The method of claim 13, wherein each coefficient matrix representing the imaging path of the projection and illumination optics of the photolithographic equipment includes transmission cross coefficients.

16. The method of claim 1, wherein the relationship representing the imaging path of the projection and illumination optics of the photolithographic equipment includes formulas including a focus, dose, numerical aperture, illumination aperture, and aberration of the photolithographic equipment.

17. The method of claim 1, wherein determining the response of the lithographic design on wafer to the change in the at least one process parameter of the photolithographic process using the first simulated image and the second simulated image further includes determining the a critical dimension sensitivity of the lithographic design to the change in the at least one process parameter of the photolithographic process.

18. The method of claim 17, wherein determining the critical dimension sensitivity of the lithographic design to the change in the at least one process parameter of the photolithographic process further includes determining a plurality of derivatives as the critical dimension sensitivity of the lithographic design.

19. The method of claim 1, wherein the change in the at least one process parameter of the photolithographic process is a change in a bias or an error in a critical dimension of a photomask containing the lithographic design.

20. A system for evaluating a response of a lithographic design on wafer to a change in at least one process parameter of a photolithographic process, wherein the photolithographic process uses photolithographic equipment, the system comprising:

a microprocessor subsystem, including a plurality of microprocessors, to convert a lithographic design to a pixel-based bitmap representation thereof, wherein the pixel-based bitmap includes pixel data, and wherein each pixel datum represents a pixel having a predetermined pixel size; and

a plurality of accelerator subsystems, each accelerator subsystem includes a plurality of programmable integrated circuits configured to process the pixel-based bitmap of the lithographic design in parallel, and each accelerator subsystem Is connected to an associated microprocessor to calculate a portion of a plurality of simulated images of the lithographic design on wafer using (1) a corresponding portion of the pixel-based bitmap representation of the lithographic design and (2) a plurality of relationships representing an imaging path of projection and illumination optics of the photolithographic process, wherein a difference between the relationships representing an imaging path of projection and illumination optics of the photolithographic process includes the at least one process parameter of the photolithographic process; and

a data processing system to determine the response of the lithographic design on wafer to the change in the at least one process parameter of the photolithographic process using the plurality of simulated images of the lithographic design on wafer.

21. The system of claim 20, wherein lithographic design includes a plurality of polygons arranged in a predetermined configuration.

22. The system of claim 21, wherein the pixel-based bitmap is a gray-level image which is representative of a plurality of polygons.

23. The system of claim 20, wherein the change in the at least one process parameter of the photolithographic process is a change in focus, illumination dose, numerical aperture or illumination aperture of the photolithographic equipment.

24. The system of claim 20, wherein the change in the at least one process parameter of the photolithographic process is a change in a bias or an error in a critical dimension of a photomask containing the lithographic design.

25. The system of claim 20, wherein the predetermined pixel size provides a sampling frequency that is greater than a Nyquist frequency in the image of the lithographic design on wafer.

26. The system of claim 20, wherein the predetermined pixel size is determined using a numerical aperture and wavelength of the projection optics of the photolithographic equipment.

27. The system of claim 20, wherein the plurality of relationships representing the imaging path of the projection and illumination optics includes a coefficient matrix representing the imaging path of the projection and illumination optics of the photolithographic equipment.

28. The system of claim 27, wherein the coefficient matrix representing the imaging path of the projection and illumination optics of the photolithographic equipment is representative of one or more of a focus, dose, numerical aperture, illumination aperture, and aberration of the photolithographic equipment.

29. The system of claim 28, wherein the coefficient matrix representing the imaging path of the projection and illumination optics of the photolithographic equipment are transmission cross coefficients.

30. The system of claim 20, wherein the system determines a set of parameters representing the imaging path of the projection and illumination optics of the photolithographic process using the one or more of a focus, dose, numerical aperture, illumination aperture, and aberration of the photolithographic equipment.

31. The system of claim 20, wherein lithographic design is a localized region of an integrated circuit design.

32. The system of claim 20, wherein the data processing system calculates settings of the photolithographic equipment using the determination of the response of the lithographic design on wafer to the change in the at least one process parameter of the photolithographic process.

33. The system of claim 32, wherein the settings of the photolithographic equipment include at least one of the focus, illumination dose, numerical aperture or illumination aperture of the photolithographic equipment.

34. The system of claim 20, wherein the lithographic design includes resolution enhancement technology.

35. The system of claim 20, wherein the data processing system determines the a critical dimension sensitivity of the lithographic design on wafer to the change in the at least one process parameter of the photolithographic process using the plurality of simulated images.

36. The system of claim 35, wherein the critical dimension sensitivity of the lithographic design to the change in the at least one process parameter of the photolithographic process includes a plurality of derivatives as the critical dimension sensitivity of the lithographic design.

37. The system of claim 20, wherein the data processing system determines a set of parameters of the projection and illumination optics of the photolithographic process using the response of the lithographic design on wafer to the change in the at least one process parameter of the photolithographic process using the plurality of simulated images of the lithographic design on wafer.

38. The system of claim 20, wherein the data processing system detects an error in the lithographic design based on the response of the lithographic design on wafer to the change in the at least one process parameter of the photolithographic process using the plurality of simulated images of the lithographic design on wafer.

39. The system of claim 38, wherein, in response to detecting the error, the data processing system determines a modification to the lithographic design to correct the error in the lithographic design on wafer.

40. The system of claim 38, wherein, in response to detecting the error, the data processing system determines a modification to at least one parameter of the projection and illumination optics of the photolithographic process to correct the error in the lithographic design on wafer.

41. A method for evaluating a response of a lithographic design on wafer to changes in a plurality of process parameters of a photolithographic process, the method comprising:

generating a pixel-based bitmap representation of a lithographic design, wherein the pixel-based bitmap includes pixel data, and wherein each pixel datum represents a pixel having a predetermined pixel size;

generating a plurality of simulated images of the lithographic design on wafer using (1) the pixel-based bitmap representation of the lithographic design and (2) a plurality of relationships representing an imaging path of projection and illumination optics of the photolithographic process wherein at least one relationship representing the imaging path of the projection and illumination optics of the photolithographic process is different from another relationship representing an imaging path of projection and illumination optics of the photolithographic process and wherein the difference includes the process parameters of the photolithographic process; and

determining the response of the lithographic design on wafer to the changes in the plurality of process parameters of the photolithographic process using the plurality of simulated images of the lithographic design on wafer.

42. The method of claim 41, wherein lithographic design includes a plurality of polygons arranged in a predetermined configuration.

43. The method of claim 41, wherein the changes in the plurality of process parameters include at least two of a change in focus, illumination dose, numerical aperture and illumination aperture of the photolithographic equipment.

44. The method of claim 41, wherein the changes in the plurality of process parameters of the photolithographic process includes a change in a bias or an error in a critical dimension of a photomask containing the lithographic design.

45. The method of claim 41, wherein lithographic design is a localized region of an integrated circuit design.

46. The method of claim 41, further including determining a configuration of settings of the photolithographic equipment using the determination of the response of the lithographic design on wafer to the changes in the plurality of process parameters of the photolithographic process.

47. The method of claim 46, wherein the configuration of settings of the photolithographic equipment includes at least two of the focus, illuminator dose, numerical aperture or illumination aperture of the photolithographic equipment.

48. The method of claim 41, wherein the pixel-based bitmap is a gray-level image which is representative of a plurality of polygons.

49. The method of claim 41, wherein the predetermined pixel size provides a sampling frequency that is greater than a Nyquist frequency in the image of the lithographic design on wafer.

50. The method of claim 41, wherein the predetermined pixel size is determined using a numerical aperture and wavelength of projection optics of the photolithographic equipment.

51. The method of claim 41, wherein the lithographic design includes resolution enhancement technology.

52. The method of claim 41, wherein the plurality of relationships representing the imaging path of the projection and illumination optics each include a coefficient matrix representing the imaging path of the projection and illumination optics of the photolithographic equipment.

53. The method of claim 41, wherein determining the response of the lithographic design on wafer to changes in the plurality of process parameters of the photolithographic process using the plurality of simulated images includes determining a critical dimension sensitivity of the lithographic design to the changes in the plurality of process parameters of the photolithographic process.

54. The method of claim 53, wherein determining the critical dimension sensitivity of the lithographic design to the changes in the process parameters of the photolithographic process further includes determining a plurality of derivatives as the critical dimension sensitivity of the lithographic design.