Method of producing of circuit board; for semiconductor device

• US 7,114,251 B2
• Filed: 05/15/2002
• Issued: 10/03/2006
• Est. Priority Date: 05/21/2001
• Status: Active Grant

• Current Assignee: Shinko Electric Industries Company Limited (Fujitsu Limited)
• Original Assignee: Shinko Electric Industries Company Limited (Fujitsu Limited)
• Inventors: Mashino, Naohiro
• Primary Examiner(s): TRINH, MINH N
• Application Number:
  US10/145,021
• Publication Number:
  US 20020170173A1
• Time in Patent Office: 1,602 Days
• Field of Search: 29829-834, 29846-847, 298/52, 257758-767, 438625-628, 438/687, 438/660, 438637-638, 438/691, 205/137, 205/123, 174255-262, 427/97, 427/98.1
• US Class Current: 29/852
• CPC Class Codes: H01L 21/288 from a liquid, e.g. electrolytic deposition
• CPC Class Codes: H01L 21/2885 using an external electrical current, i.e. electro-deposition
• CPC Class Codes: H01L 21/32115 Planarisation
• CPC Class Codes: H01L 21/3212 by chemical mechanical polishing [CMP]
• CPC Class Codes: H01L 21/4846 Leads on or in insulating or insulated substrates, e.g. metallisation H01L21/4821 takes precedence; metallisation of ceramics in general C04B41/51; printed circuits H05K3/00
• CPC Class Codes: H01L 21/486 Via connections through the substrate with or without pins
• CPC Class Codes: H01L 21/76898 formed through a semiconductor substrate
• CPC Class Codes: H01L 2224/16 of an individual bump connector
• CPC Class Codes: H01L 25/0657 Stacked arrangements of devices
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/01004 Beryllium [Be]
• CPC Class Codes: H01L 2924/01019 Potassium [K]
• CPC Class Codes: H01L 2924/01078 Platinum [Pt]
• CPC Class Codes: H01L 2924/01079 Gold [Au]
• CPC Class Codes: H01L 2924/10253 Silicon [Si]
• CPC Class Codes: H01L 2924/15311 being a ball array, e.g. BGA
• CPC Class Codes: H05K 1/0306 Inorganic insulating substrates, e.g. ceramic, glass
• CPC Class Codes: H05K 2201/0376 Flush conductors, i.e. flush with the surface of the printed circuit
• CPC Class Codes: H05K 2201/09036 Recesses or grooves in insulating substrate
• CPC Class Codes: H05K 2201/09563 Metal filled via
• CPC Class Codes: H05K 2203/0143 : Using a roller; Specific shape thereof; Providing locally adhesive portions thereon
• CPC Class Codes: H05K 2203/1509 : Horizontally held PCB
• CPC Class Codes: H05K 3/045 : by making a conductive layer having a relief pattern, followed by abrading of the raised portions
• CPC Class Codes: H05K 3/107 : by filling grooves in the support with conductive material H05K3/045, H05K3/101, H05K3/1258 and H05K3/465 take precedence
• CPC Class Codes: H05K 3/388 : by the use of a metallic or inorganic thin film adhesion layer
• CPC Class Codes: H05K 3/423 : characterised by electroplating method
• CPC Class Codes: H05K 3/4608 : comprising an electrically conductive base or core
• CPC Class Codes: Y10T 29/49155 : Manufacturing circuit on or in base
• CPC Class Codes: Y10T 29/49156 : with selective destruction of conductive paths
• CPC Class Codes: Y10T 29/49165 : by forming conductive walled aperture in base

Abstract

A method of production of a circuit board able to prevent peeling of a conductive layer during polishing of the conductive layer including the steps of forming at least holes in one surface of a substrate; forming a plating power supply layer on the one surface of the substrate, the other surface, the sides, and inner surfaces of the holes; forming a metal layer formed on the one surface of the substrate, the other surface, and the sides and burying the holes by electroplating through the plating power supply layer; and polishing the metal layer to form interconnect patterns comprised of the metal layer buried in the holes.

Claims

1. A method of production of a circuit board, including:

forming a plurality of holes in a first surface of a substrate;

forming a plating power supply layer on the first surface, a second surface and sides of the substrate, and inner surfaces of the holes by electroless plating;

forming a metal layer formed on the first surface, the second surface and sides of the substrate and burying the holes, by electroplating through the plating power supply layer; and

polishing the metal layer to form interconnect patterns comprised of the metal layer buried in the holes.

2. The method of production of a circuit board as set forth in claim 1, wherein the step of forming the metal layer is performed by connecting a power supply electrode for supplying plating current to the plating power supply layer to the plating power supply layer and changing the position of the connection of the power supply electrode.

3. The method of production of a circuit board as set forth in claim 1, further having a step of roughening the first surface of the substrate before the step of forming the holes in the substrate.

4. The method of production of a circuit board as set forth in claim 1, wherein the step of forming the holes in the substrate includes a step of forming dummy holes at least at a periphery of said substrate.

5. The method of production of a circuit board as set forth in claim 1, wherein said substrate is a silicon substrate and said method further includes a step of forming a silicon oxide film on at least the first surface and inner surface of the holes of the silicon substrate after the step of forming the holes in the substrate and before the step of forming the plating power supply layer.

6. The method of production of a circuit board as set forth in claim 1, wherein said substrate is a glass substrate.

7. The method of production of a circuit board as set forth in claim 1, wherein said plating power supply layer is comprised of a nickel (Ni) layer and a gold (Au) layer in that order from a plating substrate.