Method for integrated circuit fabrication using pitch multiplication

• US 7,115,525 B2
• Filed: 09/02/2004
• Issued: 10/03/2006
• Est. Priority Date: 09/02/2004
• Status: Expired due to Fees

• Current Assignee: Round Rock Research LLC
• Original Assignee: Micron Technology, Inc.
• Inventors: Sandhu, Gurtej, Abatchev, Mirzafer K., Tran, Luan, Durcan, D. Mark, Rericha, William T.
• Primary Examiner(s): Everhart, Caridad
• Application Number:
  US10/934,778
• Publication Number:
  US 20060046484A1
• Time in Patent Office: 761 Days
• Field of Search: 438/689, 438/950, 438/709, 438/725, 257/E21.033, 257/E21.024, 257/E21.026, 257/E21.027, 257/E21.032
• US Class Current: 438/725
• CPC Class Codes: H01L 21/0332 characterised by their composition, e.g. multilayer masks, materials
• CPC Class Codes: H01L 21/0337 characterised by the process involved to create the mask, e.g. lift-off masks, sidewalls, or to modify the mask, e.g. pre-treatment, post-treatment
• CPC Class Codes: H01L 21/0338 Process specially adapted to improve the resolution of the mask
• CPC Class Codes: H01L 21/3081 characterised by their composition, e.g. multilayer masks, materials
• CPC Class Codes: H01L 21/3086 characterised by the process involved to create the mask, e.g. lift-off masks, sidewalls, or to modify the mask, e.g. pre-treatment, post-treatment
• CPC Class Codes: H01L 21/3088 Process specially adapted to improve the resolution of the mask
• CPC Class Codes: H01L 21/31144 using masks
• CPC Class Codes: H01L 21/32139 using masks
• CPC Class Codes: Y10S 438/947 Subphotolithographic processing
• CPC Class Codes: Y10S 438/95 Multilayer mask including nonradiation sensitive layer

Abstract

Different sized features in the array and in the periphery of an integrated circuit are patterned on a substrate in a single step. In particular, a mixed pattern, combining two separately formed patterns, is formed on a single mask layer and then transferred to the underlying substrate. The first of the separately formed patterns is formed by pitch multiplication and the second of the separately formed patterns is formed by conventional photolithography. The first of the separately formed patterns includes lines that are below the resolution of the photolithographic process used to form the second of the separately formed patterns. These lines are made by forming a pattern on photoresist and then etching that pattern into an amorphous carbon layer. Sidewall pacers having widths less than the widths of the un-etched parts of the amorphous carbon are formed on the sidewalls of the amorphous carbon. The amorphous carbon is then removed, leaving behind the sidewall spacers as a mask pattern. Thus, the spacers form a mask having feature sizes less than the resolution of the photolithography process used to form the pattern on the photoresist. A protective material is deposited around the spacers. The spacers are further protected using a hard mask and then photoresist is formed and patterned over the hard mask. The photoresist pattern is transferred through the hard mask to the protective material. The pattern made out by the spacers and the temporary material is then transferred to an underlying amorphous carbon hard mask layer. The pattern, having features of difference sizes, is then transferred to the underlying substrate.

Claims

1. A method for semiconductor processing, comprising:

providing a substrate, wherein a primary mask layer overlies the substrate, wherein a temporary layer overlies the primary mask layer, wherein a first photoresist layer overlies the temporary layer;

forming a photoresist pattern in the first photoresist layer;

forming a first pattern in the temporary layer, wherein features of the first pattern are derived from features of the photoresist pattern;

forming a second photoresist layer above a level of the first pattern;

forming an other photoresist pattern in the second photoresist layer;

transferring the other photoresist pattern and the first pattern to the primary mask layer to form a mixed pattern in the primary mask layer; and

processing the substrate through the mixed pattern in the primary mask layer.

2. The method of claim 1, wherein processing the substrate comprises transferring the mixed pattern to the substrate by etching the substrate.

3. The method of claim 1, wherein forming a photoresist pattern and/or forming an other photoresist pattern comprise performing electron beam lithography.

4. The method of claim 1, wherein forming a photoresist pattern and forming an other photoresist pattern comprise performing photolithography with light having a wavelength chosen from the group consisting of 13.7 nm, 157 nm, 193 nm, 248 nm or 365 nm wavelength light.

5. The method of claim 4, wherein the first and the second photoresist layer comprise the same photoresist material.

6. The method of claim 4, wherein forming the first pattern further comprises reducing a width of the photoresist, remaining after performing photolithography, to a desired width by isotropically etching the photoresist.

7. The method of claim 6, wherein the first pattern follows an outline of lines of photoresist remaining after isotropically etching, wherein forming the first pattern comprises:

etching the temporary layer through the photoresist layer;

forming spacers on sidewalls of remains of the temporary layer after etching the temporary layer; and

preferentially removing temporary layer material relative to the spacers, wherein the spacers form the first pattern.

8. The method of claim 1, wherein the temporary layer comprises amorphous carbon.

9. The method of claim 8, wherein the primary mask layer comprises amorphous carbon.

10. The method of claim 9, wherein hard mask layers directly overlie the temporary layer and the primary mask layer.

11. The method of claim 10, wherein the hard mask layers comprise a material selected from the group consisting of silicon, silicon dioxide or an antireflective coating material.

12. The method of claim 11, wherein the antireflective coating material is a dielectric antireflective coating.

13. The method of claim 1, wherein the temporary layer comprises a bottom anti-flective coating.

14. The method of claim 13, wherein the second photoresist layer directly contacts and overlies the bottom anti-flective coating.

15. The method of claim 1, wherein the substrate is an insulator.

16. The method of claim 15, wherein processing the substrate defines conductive lines of an array of a memory device.