Strained silicon fin structure

• US 7,115,945 B2
• Filed: 01/06/2006
• Issued: 10/03/2006
• Est. Priority Date: 06/23/2003
• Status: Expired due to Term

• Current Assignee: Microsoft Technology Licensing LLC (Microsoft Corporation)
• Original Assignee: Sharp Laboratories of America Incorporated (Hon Hai Precision Industry Co., Ltd.)
• Inventors: Maa, Jer-Shen, Lee, Jong-Jan, Hsu, Sheng Teng, Tweet, Douglas J.
• Primary Examiner(s): Jackson, Jerome
• Assistant Examiner(s): Budd, Paul
• Application Number:
  US11/327,092
• Publication Number:
  US 20060113522A1
• Time in Patent Office: 270 Days
• Field of Search: 257/263, 257/627, 257/328, 257/329
• US Class Current: 257/329
• CPC Class Codes: H01L 29/1054 with a variation of the composition, e.g. channel with strained layer for increasing the mobility
• CPC Class Codes: H01L 29/66795 with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/785 having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/78687 with a multilayer structure or superlattice structure

Abstract

Disclosing is a strained silicon finFET device having a strained silicon fin channel in a double gate finFET structure. The disclosed finFET device is a double gate MOSFET consisting of a silicon fin channel controlled by a self-aligned double gate for suppressing short channel effect and enhancing drive current. The silicon fin channel of the disclosed finFET device is a strained silicon fin channel, comprising a strained silicon layer deposited on a seed fin having different lattice constant, for example, a silicon layer deposited on a silicon germanium seed fin, or a carbon doped silicon layer deposited on a silicon seed fin. The lattice mismatch between the silicon layer and the seed fin generates the strained silicon fin channel in the disclosed finFET device to improve hole and electron mobility enhancement, in addition to short channel effect reduction characteristic inherently in a finFET device.

Claims

1. A strained silicon fin structure comprising

an insulator substrate:

a silicon seed fin structure disposed on the substrate;

an underseed layer disposed between the seed fin structure and the substrate, the underseed layer material having a lattice constant different than that of the seed fin material, whereby the seed fin structure is under strain due to the lattice mismatch between the underseed layer material and the seed fin material;

a strained channel layer fabricated on the seed fin structure, the channel layer material having a lattice constant different than that of the seed fin material, and

whereby the channel layer strain is the result of the lattice mismatch between the channel layer material and the seed fin material.

2. A strained silicon fin structure as in claim 1 further comprising a hard mask insulator layer on the seed fin structure.

3. A strained silicon finFET device comprising

an insulator substrate;

a source and a drain sandwiching a strained channel region disposing on the substrate, the strained channel comprising

a seed fin structure;

an underseed layer disposed between the seed fin structure and the substrate, the underseed layer material having a lattice constant different than that of the seed fin material, whereby the seed fin structure is under strain due to the lattice mismatch between the underseed layer material and the seed fin material;

a strained channel material having a lattice constant different than that of the seed fin material;

a gate dielectric layer disposed on the strained channel; and

a gate over the strained channel and electrically isolated therefrom by the gate dielectric.

4. A strained silicon finFET device as in claim 3 wherein the seed fin structure material is silicon germanium or silicon.

5. A strained silicon finFET device as in claim 3 wherein the channel layer material is epitaxial silicon, epitaxial silicon germanium, epitaxial carbon doped silicon, or epitaxial carbon doped silicon germanium.

6. A strained silicon finFET device as in claim 3 further comprising a hard mask insulator layer on the seed fin structure.

7. A strained silicon finFET device as in claim 3 further comprising doping implantation for the strained channel and the source and drain.

8. A strained silicon finFET device as in claim 3 wherein the source region and the drain region include a lightly doped region extending to the channel region.

9. A strained silicon finFET device as in claim 3 further comprising silicidation of the gate, source and drain.