System and method for ESD protection

• US 7,115,952 B2
• Filed: 07/01/2005
• Issued: 10/03/2006
• Est. Priority Date: 11/12/1998
• Status: Expired due to Term

• Current Assignee: Avago Technologies International Sales Pte Limited (Broadcom, Inc.)
• Original Assignee: Broadcom Corporation (Broadcom, Inc.)
• Inventors: Lu, Fang, Woo, Agnes N., Kindsfater, Kenneth R.
• Primary Examiner(s): WOJCIECHOWICZ, EDWARD JOSEPH
• Application Number:
  US11/171,325
• Publication Number:
  US 20050236673A1
• Time in Patent Office: 459 Days
• Field of Search: 257/355, 257/356, 257/357, 257/360, 257/455
• US Class Current: 257/355
• CPC Class Codes: H01F 17/0006 Printed inductances printed coils for dynamo-electric machines H02K3/26; printed circuits H05K
• CPC Class Codes: H01F 17/0013 with stacked layers
• CPC Class Codes: H01F 2017/0053 with means to reduce eddy currents
• CPC Class Codes: H01F 2021/125 Printed variable inductor with taps, e.g. for VCO
• CPC Class Codes: H01L 23/50 for integrated circuit devices, e.g. power bus, number of leadsH01L23/482 - H01L23/498 take precedence
• CPC Class Codes: H01L 23/5227 Inductive arrangements or effects of, or between, wiring layers other inductive arrangements H01L23/645
• CPC Class Codes: H01L 23/60 Protection against electrostatic charges or discharges, e.g. Faraday shields
• CPC Class Codes: H01L 27/0248 for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
• CPC Class Codes: H01L 27/0251 for MOS devices
• CPC Class Codes: H01L 27/08 including only semiconductor components of a single kind
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H01L 2924/3011 Impedance
• CPC Class Codes: H03B 5/1212 the amplifier comprising a pair of transistors, wherein an output terminal of each being connected to an input terminal of the other, e.g. a cross coupled pair
• CPC Class Codes: H03B 5/1228 the amplifier comprising one or more field effect transistors
• CPC Class Codes: H03B 5/1243 the means comprising voltage variable capacitance diodes
• CPC Class Codes: H03B 5/364 the amplifier comprising field effect transistors H03B5/366 takes precedence
• CPC Class Codes: H03D 7/161 all the frequency changers being connected in cascade
• CPC Class Codes: H03D 7/18 Modifications of frequency-changers for eliminating image frequencies H03D7/16 takes precedence
• CPC Class Codes: H03G 1/0029 using FETs
• CPC Class Codes: H03H 11/1291 : Current or voltage controlled filters
• CPC Class Codes: H03J 1/0075 : where the receiving frequencies of the stations are stored in a permanent memory, e.g. ROM
• CPC Class Codes: H03J 2200/10 : Tuning of a resonator by means of digitally controlled capacitor bank
• CPC Class Codes: H03J 3/04 : Arrangements for compensating for variations of physical values, e.g. temperature
• CPC Class Codes: H03J 3/08 : by varying a second parameter simultaneously with the tuning, e.g. coupling bandpass filter
• CPC Class Codes: H03J 3/185 : with varactors, i.e. voltage variable reactive diodes
• CPC Class Codes: H03L 7/10 : for assuring initial synchronisation or for broadening the capture range
• CPC Class Codes: H03L 7/23 : with pulse counters or frequency dividers
• CPC Class Codes: H04B 1/28 : the receiver comprising at least one semiconductor device having three or more electrodes

Abstract

An integrated receiver with channel selection and image rejection substantially implemented on a single CMOS integrated circuit is described. A receiver front end provides programable attenuation and a programable gain low noise amplifier. Frequency conversion circuitry advantageously uses LC filters integrated onto the substrate in conjunction with image reject mixers to provide sufficient image frequency rejection. Filter tuning and inductor Q compensation over temperature are performed on chip. The filters utilize multi track spiral inductors. The filters are tuned using local oscillators to tune a substitute filter, and frequency scaling during filter component values to those of the filter being tuned. In conjunction with filtering, frequency planning provides additional image rejection. The advantageous choice of local oscillator signal generation methods on chip is by PLL out of band local oscillation and by direct synthesis for in band local oscillator. The VCOs in the PLLs are centered using a control circuit to center the tuning capacitance range. A differential crystal oscillator is advantageously used as a frequency reference. Differential signal transmission is advantageously used throughout the receiver. ESD protection is provided by a pad ring and ESD clamping structure that maintains signal integrity. Also provided are shunts at each pin to discharge ESD build up. The shunts utilize a gate boosting structure to provide sufficient small signal RF performance, and minimal parasitic loading.

Claims

1. An integrated circuit die, comprising:

a circuit core comprising a plurality of circuit blocks, each of the plurality of circuit blocks including a localized power bus and a localized ground bus;

a plurality of bonding pads surrounding the circuit core; and

a ground ring surrounding the plurality of bonding pads;

wherein each localized ground bus is coupled to the ground ring via a corresponding electrostatic discharge (ESD) protection device and wherein each ESD protection device is disposed in between two adjacent bonding pads.

2. The integrated circuit die of claim 1, wherein each ESD protection device is non-overlapping with respect to the two adjacent bonding pads between which it is disposed.

3. The integrated circuit die of claim 1, wherein each of the plurality of bonding pads is connected to the circuit core.

4. The integrated circuit die of claim 1, wherein each ESD protection device comprises a pair of anti-parallel diodes.

5. The integrated circuit die of claim 1, wherein the ground ring is coupled to one of the plurality of bonding pads for connection to a system ground.

6. The integrated circuit die of claim 1, wherein the ground ring comprises a partial ring structure, the partial ring structure including a first terminating point and a second terminating point, the first and second terminating points forming a gap for preventing the occurrence of eddy currents.

7. The integrated circuit die of claim 1, further comprising:

a power supply ring surrounding the plurality of bonding pads,

wherein each localized power bus is coupled to the power supply ring via a corresponding second ESD protection device.

8. The integrated circuit die of claim 7, wherein the power supply ring comprises a partial ring structure, the partial ring structure including a first terminating point and a second terminating point, the first and second terminating points forming a gap for preventing the occurrence of eddy currents.

9. An electrostatic discharge (ESD) protection system for an integrated circuit die that includes a circuit core and a plurality of bonding pads surrounding the circuit core, comprising:

a localized power supply bus disposed within the circuit core;

a localized ground bus disposed within the circuit core;

a ground ring disposed in an area between the plurality of bonding pads and a periphery of the integrated circuit die; and

a first ESD clamp coupled between the localized power supply bus and the ground ring for providing a low impedance discharge path between the localized ground bus and the ground ring, wherein the first ESD clamp is disposed between two adjacent bonding pads.

10. The ESD protection system of claim 9, further comprising:

a second ESD clamp coupled between the localized power supply bus and the localized ground bus for providing a low impedance discharge path between the localized power supply bus and the localized ground bus.

11. The ESD protection system of claim 9, wherein the first ESD clamp is non-overlapping with respect to the two adjacent bonding pads between which it is disposed.

12. The ESD protection system of claim 9, wherein each of the plurality of bonding pads is connected to the circuit core.

13. The ESD protection system of claim 9, wherein the first ESD clamp comprises a pair of anti-parallel diodes.

14. The ESD protection system of claim 9, wherein the ground ring is coupled to one of the plurality of bonding pads for connection to a system ground.

15. The ESD protection system of claim 9, wherein the ground ring comprises a partial ring structure, the partial ring structure including a first terminating point and a second terminating point, the first and second terminating points forming a gap for preventing the occurrence of eddy currents.

16. The ESD protection system of claim 9, further comprising:

a power supply ring disposed in an area between the plurality of bonding pads and a periphery of the integrated circuit die; and

a third ESD clamp coupled between the localized power supply bus and the power supply ring.

17. The ESD protection system of claim 16, wherein the power supply ring comprises a partial ring structure, the partial ring structure including a first terminating point and a second terminating point, the first and second terminating points forming a gap for preventing the occurrence of eddy currents.