Semiconductor device including stress inducing films formed over n-channel and p-channel field effect transistors and a method of manufacturing the same

• US 7,115,954 B2
• Filed: 06/29/2001
• Issued: 10/03/2006
• Est. Priority Date: 11/22/2000
• Status: Expired due to Term

• Current Assignee: Renesas Electronics Corporation
• Original Assignee: Renesas Technology Corporation (Renesas Electronics Corporation)
• Inventors: Nonaka, Yusuke, Shimizu, Akihiro, Ichinose, Katsuhiko, Ooki, Nagatoshi
• Primary Examiner(s): PHAM, HOAI V
• Application Number:
  US10/363,065
• Publication Number:
  US 20040029323A1
• Time in Patent Office: 1,922 Days
• Field of Search: 257/351, 257/369, 257/412, 257/413, 257/640, 438/153, 438/154, 438/199, 438/724, 438/744, 438/757, 438/791
• US Class Current: 257/369
• CPC Class Codes: H01L 21/0217 the material being a silicon nitride not containing oxygen, e.g. SixNy or SixByNz H01L21/02126 and H01L21/0214 take precedence
• CPC Class Codes: H01L 21/26586 characterised by the angle between the ion beam and the crystal planes or the main crystal surface
• CPC Class Codes: H01L 21/823807 with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
• CPC Class Codes: H01L 21/823814 with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures
• CPC Class Codes: H01L 21/823842 gate conductors with different gate conductor materials or different gate conductor implants, e.g. dual gate structures
• CPC Class Codes: H01L 21/823864 with a particular manufacturing method of the gate sidewall spacers, e.g. double spacers, particular spacer material or shape
• CPC Class Codes: H01L 21/84 the substrate being other than a semiconductor body, e.g. being an insulating body
• CPC Class Codes: H01L 27/092 complementary MIS field-effect transistors
• CPC Class Codes: H01L 27/0922 Combination of complementary transistors having a different structure, e.g. stacked CMOS, high-voltage and low-voltage CMOS
• CPC Class Codes: H01L 29/665 using self aligned silicidation, i.e. salicide formation of conductive layers comprising silicides H01L21/28518
• CPC Class Codes: H01L 29/6659 with both lightly doped source and drain extensions and source and drain self-aligned to the sides of the gate, e.g. lightly doped drain [LDD] MOSFET, double diffused drain [DDD] MOSFET
• CPC Class Codes: H01L 29/7843 the means being an applied insulating layer
• CPC Class Codes: H01L 29/7845 the means being a conductive material, e.g. silicided S/D or Gate
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

A semiconductor device has an n channel conductivity type field effect transistor having a channel formation region formed in a first region on one main surface of a semiconductor substrate and a p channel conductivity type field effect transistor having a channel formation region formed in a second region on the main surface of the semiconductor substrate, which second region is different from the first region. An internal stress generated in the channel formation region of the n channel conductivity type field effect transistor is different from an internal stress generated in the channel formation region of the p channel conductivity type field effect transistor. The internal stress generated in the channel formation region of the n channel conductivity type field effect transistor is a tensile stress, while the internal stress generated in the channel formation region of the p channel conductivity type field effect transistor is a compressive stress.

Claims

1. A semiconductor device comprising an n channel conductivity type field effect transistor having a channel formation region formed in a first region on one main surface of a semiconductor substrate and a p channel conductivity type field effect transistor having a channel formation region formed in a second region on said one main surface of the semiconductor substrate, which second region is different from the first region, wherein insulating films for self align contact are formed over the n channel and p channel conductivity type field effect transistors respectively to cover gate electrodes thereof, and

wherein the insulating film for self align contact covering the gate electrode of the n channel conductivity type field effect transistor generates a tensile stress in the channel formation region of the n channel conductivity type field effect transistor, while the insulating film for self align contact covering the gate electrode of the p channel conductivity type field effect transistor generates a compressive stress in the channel formation region of the p channel conductivity type field effect transistor.

2. A semiconductor device comprising an n channel conductivity type field effect transistor having a channel formation region formed in a first region on one main surface of a semiconductor substrate and a p channel conductivity type field effect transistor having a channel formation region formed in a second region on said one main surface of the semiconductor substrate, which second region is different from the first region, wherein films for generating a tensile stress in the channel region of the n channel conductivity type field effect transistor and a compressive stress in the channel region of the p channel conductivity type field effect transistor are formed over the n channel and p channel conductivity type field effect transistors respectively to cover gate electrodes thereof, wherein the film covering the gate electrode of the p channel conductivity type field effect transistor is formed by plasma CVD, and wherein the film covering the gate electrode of the n channel conductivity type field effect transistor is formed by thermal CVD.

3. A semiconductor device comprising an n channel conductivity type field effect transistor having a channel formation region formed in a first region on one main surface of a semiconductor substrate and a p channel conductivity type field effect transistor having a channel formation region formed in a second region on said one main surface of the semiconductor substrate, which second region is different from the first region, wherein films for generating a stress which makes an interatomic distance of silicon in the channel formation region of the n channel conductivity type field effect transistor wider than an interatomic distance of silicon in the channel formation region of the p channel conductivity type field effect transistor are formed by plasma CVD over the n channel and p channel conductivity type field effect transistors respectively to cover gate electrodes thereof.

4. A semiconductor comprising an n channel conductivity type field effect transistor having a channel formation region formed in a first region on one main surface of a semiconductor substrate and a p channel conductivity type field effect transistor having a channel formation region formed in a second region on the one main surface of the semiconductor substrate which region is different from the first region,

wherein a film for generating a tensile stress in the channel formation region of the n channel conductivity type field effect transistor is formed over a gate electrode of the n channel conductivity type field effect transistor to cover the gate electrode thereof, while a film for generating a compressive stress in the channel formation region of the p channel conductivity type field effect transistor is formed over a gate electrode of the p channel conductivity type field effect transistor to cover the gate electrode thereof.

5. A semiconductor device comprising an n channel conductivity type field effect transistor having a channel formation region formed in a first region on one main surface of a semiconductor substrate and a p channel conductivity type field effect transistor having a channel formation region formed in a second region on the one main surface of the semiconductor substrate which region is different from the first region,

wherein films for generating a stress generated in the channel formation region of the p channel conductivity type field effect transistor greater than a compressive stress generated in the channel formation region of the n channel conductivity type field effect transistor are formed over the n channel and p channel conductivity field effect transistors respectively to cover gate electrodes thereof.

6. A semiconductor device comprising an n channel conductivity type field effect transistor having a channel formation region formed in a first region on one main surface of a semiconductor substrate and a p channel conductivity type field effect transistor having a channel formation region formed in a second region on the one main surface of the semiconductor substrate which region is different from the first region,

wherein films for generating a stress to make a tensile stress generated in the channel formation region of the n channel conductivity type field effect transistor greater than a tensile stress generated in the channel formation region of the p channel type field effect transistor are formed over the n channel and p channel conductivity field effect transistors respectively to cover gate electrodes thereof.

7. A semiconductor device comprising an n channel conductivity type field effect transistor having a channel formation region formed in a first region on one main surface of a semiconductor substrate and a p channel conductivity type field effect transistor having a channel formation region formed in a second region on said one main surface of the semiconductor substrate, which second region is different from the first region, wherein the semiconductor device further comprises at least either one of a film which is formed over a gate electrode of the n channel conductivity type field effect transistor to cover the gate electrode thereof and generates a tensile stress in the channel formation region of the n channel conductivity type field effect transistor, or a film which is formed over a gate electrode of the p channel conductivity type field effect transistor to cover the gate electrode thereof and generates a compressive stress in the channel formation region of the p channel conductivity type field effect transistor.

8. A semiconductor device according to claim 7, wherein the film is a silicon nitride film.

9. A semiconductor device according to claim 7, wherein the film for generating a tensile stress in the channel formation region of the n channel conductivity type field effect transistor is a film formed over said one main surface of the semiconductor substrate to cover the n channel conductivity type field effect transistor, and

wherein the film for generating a compressive stress in the channel formation region of the p channel conductivity type field effect transistor is a film formed over said one main surface of the semiconductor substrate to cover the p channel conductivity type field effect transistor.

10. A semiconductor device according to claim 7,

wherein the film which generates a tensile stress in the channel formation region of the n channel conductivity type field effect transistor covers side wall spacers formed on the side walls of the gate electrode of the n channel conductivity type field effect transistor, and

wherein the film which generates a compressive stress in the channel formation region of the p channel conductivity type field effect transistor covers side wall spacers formed on the side walls of the gate electrode of the p channel conductivity type field effect transistor.

11. A method of manufacture of a semiconductor device having an n channel conductivity type field effect transistor having a channel formation region formed in a first region on one main surface of a semiconductor substrate and a p channel conductivity type field effect transistor having a channel formation region formed in a second region on said one main surface of the semiconductor substrate, which second region is different from the first region, the method comprising a step of forming at least either one of a film which is formed over a gate electrode of the n channel conductivity type field effect transistor to cover the gate electrode thereof and generates a tensile stress in the channel formation region of the n channel conductivity type field effect transistor or a film which is formed over a gate electrode of the p channel conductivity type field effect transistor to cover the gate electrode thereof and generates a compressive stress in the channel formation region of the p channel conductivity type field effect transistor.

12. A method of manufacture of a semiconductor device according to claim 11, wherein the film is a silicon nitride film.

13. A semiconductor device having an n channel conductivity type field effect transistor and a p channel conductivity type field effect transistor, each formed over a semiconductor substrate,

wherein films for generating a stress to make an interatomic distance of silicon in the channel formation region of the n channel conductivity type field effect transistor greater than an interatomic distance of silicon in the channel formation region of the p channel conductivity type field effect transistor are formed over the n channel and p channel conductivity type field effect transistors to cover gate electrodes thereof.

16. A semiconductor device according to any one of claims 13 to 15,

wherein the stress generated in the channel formation region of the n channel conductivity type field effect transistor is a tensile stress, while the stress generated in the channel formation region of the p channel conductivity type field effect transistor is a compressive stress.

17. A semiconductor device according to any one of claims 13 to 15,

wherein, when each of the stresses generated in the channel formation regions of the n channel conductivity type field effect transistor and the p channel conductivity type field effect transistor is a compressive stress, the compressive stress generated in the channel formation region of the p channel conductivity type field effect transistor is greater than the compressive stress generated in the channel formation region of the n channel conductivity type field effect transistor.

18. A semiconductor device according to any one of claims 13 to 15,

wherein when each of the stresses generated in the channel formation regions of the n channel conductivity type field effect transistor and the p channel conductivity type field effect transistor is a tensile stress, the tensile stress generated in the channel formation region of the n channel conductivity type field effect transistor is greater than the compressive stress generated in the channel formation region of the p channel conductivity type field effect transistor.

19. A semiconductor device according to any one of claim 13 to 15, wherein the films each covers therewith the gate electrode and side wall spacers formed over the side walls of the gate electrode.

20. A semiconductor device according to any one of claim 13 to 15, wherein the film thickness over the n channel conductivity type field effect transistor is different from the film thickness over the p channel conductivity type field effect transistor.

14. A semiconductor device having an n channel conductivity type field effect transistor and a p channel conductivity type field effect transistor, each formed over a semiconductor substrate,

wherein films for generating a stress to make an interatomic distance of silicon in the channel formation region of the n channel conductivity type field effect transistor greater than an interatomic distance of silicon in the channel formation region of the p channel conductivity type field effect transistor are formed over the n channel and p channel conductivity type field effect transistors respectively to cover gate electrodes thereof, and

wherein the films are each formed of an insulating film for self align contact.

15. A semiconductor device having an n channel conductivity type field effect transistor and a p channel conductivity type field effect transistor, each formed over a semiconductor substrate,

wherein films are formed over the n channel and p channel conductivity type field effect transistors to cover gate electrodes thereof in order to generate a stress in the channel formation regions of the n channel conductivity type field effect transistor and the p channel conductivity type field effect transistor respectively,

wherein the films generate a stress to make an interatomic distance of silicon in the channel formation region of the n channel conductivity type field effect transistor greater than an interatomic distance of silicon in the channel formation region of the p channel conductivity type field effect transistor,

wherein the film covering the gate electrode of the p channel conductivity type field effect transistor is formed by plasma CVD, and

wherein the film covering the gate electrode of the n channel conductivity type field effect transistor is formed by thermal CVD.

21. A semiconductor device having an n channel conductivity type field effect transistor and a p channel conductivity type field effect transistor, each formed over a semiconductor substrate,

wherein a film for generating a stress to make a residual stress in the direction of flow of a drain current in the channel formation region of the n channel conductivity type field effect transistor to a tensile stress is formed over a gate electrode of the n channel conductivity type field effect transistor to cover the gate electrode thereof, and

wherein the film for generating a stress to make a residual stress in the direction of flow of a drain current in a channel formation region of the p channel conductivity type field effect transistor to a compressive stress is formed over a gate electrode of the p channel conductivity type field effect transistor to cover the gate electrode thereof.

24. A semiconductor device according to any of claims 21 to 23,

wherein the films are each formed of an insulating film for self align contact.

22. A semiconductor device having an n channel conductivity type field effect transistor and a p channel conductivity type field effect transistor, each formed over a semiconductor substrate,

wherein films for generating a stress which makes a compressive stress in the direction of flow of a drain current in a channel formation region of the p channel conductivity type field effect transistor greater than a compressive stress in the direction of flow of a drain current in a channel formation region of the n channel conductivity type field effect transistor are formed over the n channel and p channel conductivity type field effect transistors respectively to cover gate electrodes thereof.

23. A semiconductor device having an n channel conductivity type field effect transistor and a p channel conductivity type field effect transistor, each formed over a semiconductor substrate,

wherein films for generating a stress to make a tensile stress in the direction of flow of a drain current in a channel formation region of the n channel conductivity type field effect transistor greater than a tensile stress in the direction of flow of a drain current in a channel formation region of the p channel conductivity type field effect transistor are formed over the n channel and p channel conductivity type field effect transistors respectively to cover gate electrodes thereof.

25. A semiconductor device having an n channel conductivity type field effect transistor and a p channel conductivity type field effect transistor, each formed over a semiconductor substrate,

wherein films for generating a stress to make an interatomic distance of silicon in the direction of flow of a drain current in a channel formation region of the n channel conductivity type field effect transistor greater than an interatomic distance of silicon in the direction of flow of a drain current in a channel formation region of the p channel conductivity type field effect transistor are formed over the n channel and p channel conductivity type field effect transistors respectively to cover gate electrodes thereof.

26. A semiconductor device having an n channel conductivity type field effect transistor and a p channel conductivity type field effect transistor, each formed over a semiconductor substrate,

wherein insulating films for self align contact are formed over the n channel and p channel conductivity type field effect transistors respectively to cover gate electrodes thereof, and

wherein the insulating films for self align contact generate a stress to make an interatomic distance of silicon in the direction of flow of a drain current in the channel formation region of the n channel conductivity type field effect transistor greater than an interatomic distance of silicon in the direction of flow of a drain current in the channel formation region of the p channel conductivity type field effect transistor.

27. A manufacturing method of a semiconductor device having an n channel conductivity type field effect transistor formed over a semiconductor substrate,

the method comprising the steps of:

forming, over a gate electrode of the p channel conductivity type field effect transistor, a film for generating a compressive stress in a channel formation region of the p channel conductivity type field effect transistor by plasma CVD to cover the gate electrode; and

forming, over a gate electrode of the n channel conductivity type field effect transistor, a film for generating a tensile stress in a channel formation region of the n channel conductivity type field effect transistor by plasma CVD to cover the gate electrode.