Lateral power MOSFET for high switching speeds

• US 7,115,958 B2
• Filed: 10/19/2004
• Issued: 10/03/2006
• Est. Priority Date: 10/29/2001
• Status: Expired due to Fees

• Current Assignee: Power Integrations Incorporated
• Original Assignee: Power Integrations Incorporated
• Inventors: Disney, Donald Ray, Grabowski, Wayne Bryan
• Primary Examiner(s): Le, Thao X.
• Application Number:
  US10/968,659
• Publication Number:
  US 20050077583A1
• Time in Patent Office: 714 Days
• Field of Search: 257401-402, 257341-343, 257/E21.435
• US Class Current: 257/401
• CPC Class Codes: H01L 29/402 Field plates
• CPC Class Codes: H01L 29/41725 Source or drain electrodes for field effect devices with monocrystalline semiconductor on source/drain region H01L29/0843
• CPC Class Codes: H01L 29/41758 for lateral devices with structured layout for source or drain region, i.e. the source or drain region having cellular, interdigitated or ring structure or being curved or angular H01L29/41733 - H01L29/4175 take precedence
• CPC Class Codes: H01L 29/41775 characterised by the proximity or the relative position of the source or drain electrode and the gate electrode, e.g. the source or drain electrode separated from the gate electrode by side-walls or spreading around or above the gate electrode
• CPC Class Codes: H01L 29/42368 the thickness being non-uniform
• CPC Class Codes: H01L 29/42372 characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out H01L29/42324 takes precedence
• CPC Class Codes: H01L 29/4238 characterised by the surface lay-out
• CPC Class Codes: H01L 29/7835 with asymmetrical source and drain regions, e.g. lateral high-voltage MISFETs with drain offset region, extended drain MISFETs

Abstract

A lateral power metal-oxide-semiconductor field effect transistor (MOSFET) having a gate structure in which the insulated gate is coupled to the gate electrode through contacts at a plurality of locations. The source electrode includes first and second segments. The first segment is interposed between the drain electrode and the gate electrode and acts as a field plate.

Claims

1. A lateral field-effect transistor comprising:

interdigitated source and drain region fingers, a source region finger being separated from a first drain region finger on a first side by a first channel region and from a second drain region finger on a second side by a second channel region;

a first gate member disposed over the first channel region and a second gate member disposed over the second channel region, the first and second gate members being substantially parallel;

a drain electrode extending substantially over, and coupled with, the first and second drain region fingers;

a gate electrode extending substantially over, and coupled with, the first gate member, the gate electrode and the drain electrode being disposed in a general plane;

a source electrode that includes first and second source electrode segments each being coupled to the source region finger and each having first and second ends, the first end of the first source electrode segment being merged with the first end of the second source electrode segment, the second end of the first source electrode segment being merged with the second end of the second source electrode segment, the first source electrode segment being disposed substantially over the source region finger and including a laterally extended portion that substantially overlaps the second gate member, the gate electrode being laterally surrounded by the first and second source electrode segments, with the first source electrode segment being adjacent a first lateral side of the gate electrode and the second source electrode segment being adjacent a second lateral side of the gate electrode; and

wherein a majority of a source current flows in the first source electrode segment, and a minority of the source current flows in the second source electrode segment, when the lateral field-effect transistor is in an on-state.

2. The lateral field-effect transistor according to claim 1 wherein the first and second gate members are connected by a bridging member.

3. A field-effect transistor comprising:

a substrate;

source and drain regions disposed in the substrate;

a gate disposed over a region of the substrate between the source and drain regions;

a drain electrode disposed substantially over, and coupled with, the drain region;

a gate electrode having first and second lateral sides disposed substantially over, and coupled with, the gate, the gate electrode and the drain electrode being disposed in a general plane;

a source electrode having first and second source electrode segments each having first and second ends, the first end of the first source electrode segment being merged with the first end of the second source electrode segment, the second end of the first source electrode segment being merged with the second end of the second source electrode segment, the first and second source electrode segments being electrically connected to the source region, the first source electrode segment being interposed between the drain electrode and a first lateral side of the gate electrode in the general plane, the second source electrode segment being disposed substantially over the source region and having a first side adjacent the second lateral side of the gate electrode, wherein a majority of a source current flows in the second source electrode segment, and a minority of the source current flows in the first source electrode segment, when the lateral field-effect transistor is in an on-state.

4. The field-effect transistor according to claim 3 wherein the gate comprises first and second gate members, the gate electrode being disposed substantially over the first gate member.

5. The field-effect transistor according to claim 4 wherein the second source electrode segment includes a field plate portion that laterally extends substantially over the second gate member.

6. The field-effect transistor according to claim 4 wherein the source electrode surrounds the gate electrode in the general plane.

7. The field-effect transistor according to claim 4 wherein the second source electrode segment is substantially wider than the first source electrode segment.

8. The field-effect transistor according to claim 3 wherein the source and drain regions are arranged in an interdigitated manner.

9. The field-effect transistor according to claim 3 wherein the drain electrode includes a field plate portion.

10. A lateral field-effect transistor comprising:

a substrate;

source and drain regions disposed in the substrate;

a first gate member disposed over a first region of the substrate between the source and drain regions, and a second gate member disposed over a second region of the substrate between the source and drain regions, the first and second gate members being substantially parallel and being connected by at least one bridging member;

a drain electrode extending substantially over the drain region, the drain electrode being electrically connected to the drain region;

a gate electrode extending substantially over the first gate member, the gate electrode being electrically connected to the first and second gate members; and

a source electrode that includes first and second source electrode segments each having first and second ends, the first end of the first source electrode segment being merged with the first end of the second source electrode segment, the second end of the first source electrode segment being merged with the second end of the second source electrode segment, the first and second source electrode segments being coupled to the source region, the first source electrode segment being disposed substantially over the source region and having a field plate that extends over the second gate member, the gate electrode being laterally surrounded by the first and second source electrode segments, with the first source electrode segment being adjacent a first lateral side of the gate electrode and the second source electrode segment being disposed between a second lateral side of the gate electrode and the drain electrode.

11. The lateral field-effect transistor according to claim 10 wherein a majority of a source current flows in the first source electrode segment, and a minority of the source current flows in the second source electrode segment, when the lateral field-effect transistor is in an on-state.

12. The lateral field-effect transistor according to claim 10 wherein the second source electrode segment and the gate electrode are disposed in a general plane.

13. The lateral field-effect transistor according to claim 10 wherein the source and drain regions are arranged in an interdigitated manner.