Apparatus to prevent damage to probe card

• US 7,116,124 B2
• Filed: 12/20/2002
• Issued: 10/03/2006
• Est. Priority Date: 06/25/2001
• Status: Expired due to Fees

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Byrd, Phillip E.
• Primary Examiner(s): Ramirez, Nestor
• Assistant Examiner(s): Nguyen, Trung Q.
• Application Number:
  US10/327,246
• Publication Number:
  US 20030122564A1
• Time in Patent Office: 1,383 Days
• Field of Search: 324/754, 324/755, 324/765, 324/763, 324/158.1, 439/14, 439/17, 174/260, 174/261, 174/255, 361/760, 361/768, 361/771, 361/779
• US Class Current: 324/750.05
• CPC Class Codes: G01R 1/06766 Input circuits therefor
• CPC Class Codes: G01R 1/07371 using an intermediate card or back card with apertures through which the probes pass
• CPC Class Codes: G01R 1/36 Overload-protection arrangements or circuits for electric measuring instruments
• CPC Class Codes: G01R 3/00 Apparatus or processes specially adapted for the manufacture or maintenance of measuring instruments , e.g. of probe tips
• CPC Class Codes: G01R 31/2886 Features relating to contacting the IC under test, e.g. probe heads; chucks G01R31/2865 takes precedence, test connections, e.g. test sockets, or probes per se, G01R1/04 or G01R1/06
• CPC Class Codes: H05K 1/0293 Individual printed conductors which are adapted for modification, e.g. fusable or breakable conductors, printed switches
• CPC Class Codes: H05K 1/09 Use of materials for the conductive, e.g. metallic pattern
• CPC Class Codes: H05K 1/167 incorporating printed resistors
• CPC Class Codes: H05K 2201/068 wherein the coefficient of thermal expansion is important
• CPC Class Codes: H05K 2201/10053 Switch
• CPC Class Codes: H05K 2201/10181 Fuse
• CPC Class Codes: Y10T 29/49004 including measuring or testing of device or component part
• CPC Class Codes: Y10T 29/49005 Acoustic transducer
• CPC Class Codes: Y10T 29/49107 Fuse making
• CPC Class Codes: Y10T 29/49117 Conductor or circuit manufacturing
• CPC Class Codes: Y10T 29/49126 Assembling bases
• CPC Class Codes: Y10T 29/4913 Assembling to base an electrical component, e.g., capacitor, etc.
• CPC Class Codes: Y10T 29/49139 by inserting component lead or terminal into base aperture
• CPC Class Codes: Y10T 29/49147 Assembling terminal to base
• CPC Class Codes: Y10T 29/49155 Manufacturing circuit on or in base
• CPC Class Codes: Y10T 29/49204 : Contact or terminal manufacturing

Abstract

Probe cards are configured with protective circuitry suitable for use in electrical testing of semiconductor dice without damage to the probe cards. Protective fuses are provided in electrical communication with conductive traces and probe elements (e.g., probe needles) of a probe card. The fuses may be active or passive fuses and are preferably self-resetting, repairable, and/or replaceable. Typically, the fuses will be interposed in, or located adjacent to, conductive traces residing over a surface of the probe card. Methods of fabricating a probe card are provided, as well as various probe card configurations. A semiconductor die testing system using the probe card is also provided.

Claims

1. A probe card used as an interface or a testing computer for testing at least one semiconductor die having at least one bond pad comprising:

a substrate having a first surface and a second surface forming surfaces of the probe card during testing of at least one semiconductor die using the testing computer;

a plurality of conductive traces disposed adjacent at least one of the first surface and the second surface, at least one conductive trace for carrying current during the testing of at least one semiconductor die using the testing computer;

a plurality of probe elements in respective electrical communication with the plurality of conductive traces, at least one probe element of the plurality of probe elements for contacting the at least one bond pad of the at least one semiconductor die during testing; and

a plurality of fuses disposed adjacent the at least one of the first surface and the second surface and in respective electrical communication with the plurality of conductive traces for conducting current below a predetermined maximum level and or preventing conducting current when the current is above a predetermined maximum level during the testing of the at least one semiconductor die.

2. The probe card of claim 1, wherein at least one fuse of the plurality of fuses is configured to be replaceable or repairable after being tripped by an electrical current supplied thereto.

3. The probe card of claim 1, wherein at least one fuse of the plurality of fuses is configured of a material selected from the group consisting of titanium tungsten, aluminum, platinum silicide, copper, nichrome, doped polysilicon, metal silicide, and alloys of any thereof.

4. The probe card of claim 1, wherein at least one of the plurality of fuses and at least one of the plurality of conductive traces are constructed of the same materials.

5. The probe card of claim 1, wherein at least one of the plurality of fuses and at least one of the plurality of conductive traces are constructed over a surface of the probe card during a single deposition process.

6. The probe card of claim 1, wherein each of the plurality of fuses is fabricated of the same materials in a single deposition process.

7. The probe card of claim 1, wherein at least one fuse of the plurality of fuses is configured as a dual in-line pin header fuse.

8. The probe card of claim 1, wherein at least one fuse of the plurality of fuses is configured as a dual in-line socket fuse.

9. The probe card of claim 1, wherein at least one fuse of the plurality of fuses is configured to be self-resetting after being tripped.

10. The probe card of claim 9, wherein the at least one fuse is configured as a PPTC fuse.

11. The probe card of claim 9, wherein the at least one fuse is configured as a bimetallic switch.

12. The probe card of claim 1, wherein at least one fuse of the plurality of fuses is configured as a passive fuse.

13. The probe card of claim 1, wherein each of the plurality of conductive traces is in electrical communication with a respective fuse of the plurality of fuses.

14. The probe card of claim 1, wherein each of the plurality of fuses is disposed adjacent a peripheral region of the substrate.

15. The probe card of claim 1, wherein the probe card is configured as a probe card selected from the group consisting of vertical contact probe cards, cantilever-type probe cards, and probe cards for wafer level burn-in.

16. The probe card of claim 1, further comprising at least one electrical component selected from the group consisting of resistors, transistors, capacitors, and diodes in electrical communication with at least one conductive trace of the plurality of conductive traces.

17. The probe card of claim 1, wherein at least one fuse of the plurality of fuses is configured as a discrete electrical component.

18. The probe card of claim 17, wherein the discrete electrical component is affixed in a surface mount configuration to a portion of the probe card.

19. The probe card of claim 1, wherein at least one conductive trace of the plurality of conductive traces is disposed in a layer proximately underneath the at least one of the first surface and second surface of the substrate.

20. The probe card of claim 1, wherein at least one fuse of the plurality of fuses is located directly adjacent a probe element of the plurality of probe elements.

21. The probe card of claim 1, wherein each fuse of the plurality of fuses is in electrical communication with a respective probe element of the plurality of probe elements.

22. The probe card of claim 1, wherein the plurality of probe elements is configured in a pattern for simultaneously testing integrated circuitry of a plurality of semiconductor dice.

23. The probe card of claim 1, further comprising a test contact in electrical communication with a conductive trace of the plurality of conductive traces, the test contact configured for supplying a current to the conductive trace of the plurality of conductive traces, and wherein at least one fuse of the plurality of fuses is interposed adjacently between the test contact and the conductive trace of the plurality of conductive traces.

24. A probe card comprising:

a substrate having a first surface and a second surface forming surfaces of the probe card;

a plurality of conductive traces disposed adjacent at least one of the first surface and the second surface;

a plurality of probe elements in respective electrical communication with the plurality of conductive traces; and

a plurality of fuses disposed adjacent the at least one of the first surface and the second surface and in respective electrical communication with the plurality of conductive traces, at least one fuse of the plurality of fuses configured as a discrete electrical component, the discrete electrical component mounted by conductive pins into through-hole portions of the surfaces of the probe card.

25. A probe card having a substrate having a first surface and a second surface used as an interface for a testing computer for testing at least one semiconductor die having at least one bond pad comprising:

a plurality of conductive traces disposed adjacent at least one of the first surface and the second surface, at least one conductive trace for carrying current during the testing of the at least one semiconductor die using the testing computer;

a plurality of probe elements in respective electrical communication with the plurality of conductive traces, at least one probe element of the plurality of probe elements for contacting the at least one bond pad of the at least one semiconductor die during the testing; and

a plurality of fuses disposed adjacent the at least one of the first surface and the second surface and in respective electrical communication with the plurality of conductive traces for conducting current below a predetermined maximum level and or preventing conducting current when the current is above a predetermined maximum level during the testing of the at least one semiconductor die.

26. The probe card of claim 25, wherein at least one fuse of the plurality of fuses is configured to be replaceable or repairable after being tripped by an electrical current supplied thereto.

27. The probe card of claim 25, wherein at least one fuse of the plurality of fuses is configured of a material selected from the group consisting of titanium tungsten, aluminum, platinum suicide, copper, nichrome, doped polysilicon, metal suicide, and alloys of any thereof.

28. The probe card of claim 25, wherein at least one of the plurality of fuses and at least one of the plurality of conductive traces are constructed of the same materials.

29. The probe card of claim 25, wherein at least one of the plurality of fuses and at least one of the plurality of conductive traces are constructed over a surface of the probe card during a single deposition process.

30. The probe card of claim 25, wherein each of the plurality of fuses is fabricated of the same materials in a single deposition process.

31. The probe card of claim 25, wherein at least one fuse of the plurality of fuses is configured as a dual in-line pin header fuse.

32. The probe card of claim 25, wherein at least one fuse of the plurality of fuses is configured as a dual in-line socket fuse.

33. The probe card of claim 25, wherein at least one fuse of the plurality of fuses is configured to be self-resetting after being tripped.

34. The probe card of claim 33, wherein the at least one fuse is configured as a PPTC fuse.

35. The probe card of claim 33, wherein the at least one fuse is configured as a bimetallic switch.

36. The probe card of claim 25, wherein at least one fuse of the plurality of fuses is configured as a passive fuse.

37. The probe card of claim 25, wherein each of the plurality of conductive traces is in electrical communication with a respective fuse of the plurality of fuses.

38. The probe card of claim 25, wherein each of the plurality of fuses is disposed adjacent a peripheral region of the substrate.

39. The probe card of claim 25, wherein the probe card is configured as a probe card selected from the group consisting of vertical contact probe cards, cantilever-type probe cards, and probe cards for wafer level burn-in.

40. The probe card of claim 25, further comprising at least one electrical component selected from the group consisting of resistors, transistors, capacitors, and diodes in electrical communication with at least one conductive trace of the plurality of conductive traces.

41. The probe card of claim 25, wherein at least one fuse of the plurality of fuses is configured as a discrete electrical component.

42. The probe card of claim 41, wherein the discrete electrical component is affixed in a surface mount configuration to a portion of the probe card.

43. The probe card of claim 25, wherein at least one conductive trace of the plurality of conductive traces is disposed in a layer proximately underneath the at least one of the first surface and second surface of the substrate.

44. The probe card of claim 25, wherein at least one fuse of the plurality of fuses is located directly adjacent a probe element of the plurality of probe elements.

45. The probe card of claim 25, wherein each fuse of the plurality of fuses is in electrical communication with a respective probe element of the plurality of probe elements.

46. The probe card of claim 25, wherein the plurality of probe elements is configured in a pattern for simultaneously testing integrated circuitry of a plurality of semiconductor dice.

47. The probe card of claim 25, further comprising a test contact in electrical communication with a conductive trace of the plurality of conductive traces, the test contact configured for supplying a current to the conductive trace, and wherein at least one fuse of the plurality of fuses is interposed adjacently between the test contact and the conductive trace.

48. A probe card having a substrate having a first surface and a second surface comprising:

a plurality of conductive traces disposed adjacent at least one of the first surface and the second surface;

a plurality of probe elements in respective electrical communication with the plurality of conductive traces; and

a plurality of fuses disposed adjacent the at least one of the first surface and the second surface and in respective electrical communication with the plurality of conductive traces, at least one fuse of the plurality of fuses configured as a discrete electrical component, the discrete electrical component mounted by conductive pins into through-hole portions of a surface of the probe card.