Level converter circuit, display device and portable terminal device

• US 7,116,307 B2
• Filed: 10/18/2002
• Issued: 10/03/2006
• Est. Priority Date: 10/19/2001
• Status: Active Grant

• Current Assignee: Japan Display West Incorporated (Japan Display Incorporated)
• Original Assignee: Sony Corporation (Sony Group Corp.)
• Inventors: Nakajima, Yoshiharu, Toyozawa, Noboru
• Primary Examiner(s): Eisen, Alexander
• Application Number:
  US10/450,935
• Publication Number:
  US 20040041777A1
• Time in Patent Office: 1,446 Days
• Field of Search: 345 87-102, 345204-213
• US Class Current: 345/100
• CPC Class Codes: G09G 2300/0408 Integration of the drivers onto the display substrate
• CPC Class Codes: G09G 2300/0814 used for selection purposes, e.g. logical AND for partial update
• CPC Class Codes: G09G 2300/0842 forming a memory circuit, e.g. a dynamic memory with one capacitor
• CPC Class Codes: G09G 2310/0232 Special driving of display border areas
• CPC Class Codes: G09G 2310/0289 Details of voltage level shifters arranged for use in a driving circuit
• CPC Class Codes: G09G 2310/0297 Special arrangements with multiplexing or demultiplexing of display data in the drivers for data electrodes, in a pre-processing circuitry delivering display data to said drivers or in the matrix panel, e.g. multiplexing plural data signals to one D/A converter or demultiplexing the D/A converter output to multiple columns
• CPC Class Codes: G09G 2310/08 Details of timing specific for flat panels, other than clock recovery
• CPC Class Codes: G09G 2330/021 Power management, e.g. power saving
• CPC Class Codes: G09G 3/20 for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
• CPC Class Codes: G09G 3/3659 the addressing of the pixel involving the control of two or more scan electrodes or two or more data electrodes, e.g. pixel voltage dependant on signal of two data electrodes
• CPC Class Codes: G09G 3/3688 suitable for active matrices only
• CPC Class Codes: H03K 19/0016 by using a control or a clock signal, e.g. in order to apply power supply
• CPC Class Codes: H03K 3/356113 using additional transistors in the input circuit

Abstract

This invention realizes reduction in consumption of DC current in a level converter circuit by setting level shifters in an operating state only when necessary in accordance with hierarchical control, in which an output pulse of a level shifter (311) that is constantly in a power-ON state is used to set a level shifter (321) of the next hierarchical level in the operating state, then output pulses of the level shifter (311) and the level shifter (321) are used to generate control pulses LT1 and LT2, which are used to set level shifters (341 to 346) of the next hierarchical level in the operating state, and an output pulse of one of the level shifters is used to set level shifters (351), (352) and (353) of the next hierarchical level in the operating state. Thus, a level converter circuit in which the consumption of DC current is reduced and which enables reduction in power consumption of the whole device, a display device equipped with this level converter circuit, and a portable telephone device using the display device as an output display unit can be constructed.

Claims

1. A level converter circuit comprising:

a first circuit that is constantly in an operating state and performs level conversion of a first timing pulse that becomes active for a predetermined period, from a first voltage amplitude to a second voltage amplitude; and

a second circuit that is in an operating state during an active period of the first timing pulse using the first timing pulse after the level conversion by the first circuit and performs level conversion of a second timing pulse from the first voltage amplitude to the second voltage amplitude further comprising;

a timing control circuit for generating a control pulse that becomes active during the active period of the first timing pulse on the basis of the first and second timing pulses after the level conversion by the first and second circuits; and

a third circuit that is in an operating state during an active period of the control pulse using the control pulse and performs level conversion of a third timing pulse from the first voltage amplitude to the second voltage amplitude.

2. The level converter circuit as claimed in claim 1 wherein the third circuit includes plural circuit parts corresponding to plural said third timing pulses.

3. The level converter circuit as claimed in claim 1, wherein the timing control circuit generates first and second control pulses that become active at different timing during the active period of the first timing pulse, and

the third circuit is a sampling latch-type level shifter that is in a non-operating state during an active period of one of the first and second control pulses that is generated first and then takes the third timing pulse therein, and that is in an operating state when the control pulse is inactive, then latches the control pulse, and latches the latched data on a subsequent stage synchronously with the control pulse that is generated later.

4. The level converter circuit as claimed in claim 1 further comprising a fourth circuit that is in an operating state during an active period of the third timing pulse using the third timing pulse after the level conversion by the third circuit and performs level conversion of a fourth timing pulse from the first voltage amplitude to the second voltage amplitude.

5. The level converter circuit as claimed in claim 4 wherein the fourth circuit includes plural circuit parts corresponding to plural said fourth timing pulses.

6. A display device comprising a pixel unit having pixels arrayed in a matrix on a board, driving means provided on the same board as the pixel unit and adapted for driving the pixels of the pixel unit, and a level converter circuit for performing level conversion of a timing pulse of a first voltage amplitude inputted from outside the board to a second voltage amplitude and supplying the level-converted timing pulse to the driving means,

the level converter circuit comprising:

a first circuit that is constantly in an operating state and performs level conversion of a first timing pulse that becomes active during a horizontal blanking period of an image signal, from the first voltage amplitude to the second voltage amplitude; and

a second circuit that is in an operating state during an active period of the first timing pulse using the first timing pulse after the level conversion by the first circuit and performs level conversion of a second timing pulse from the first voltage amplitude to the second voltage amplitude wherein the level converter circuit further comprises;

a timing control circuit for generating a control pulse that becomes active during the active period of the first timing pulse on the basis of the first and second timing pulses after the level conversion by the first and second circuits; and

a third circuit that is in an operating state during an active period of the control pulse using the control pulse and performs level conversion of a third timing pulse from the first voltage amplitude to the second voltage amplitude.

7. The display device as claimed in claim 6 wherein the third circuit includes plural circuit parts corresponding to plural said third timing pulses.

8. The display device as claimed in claim 6 wherein the timing control circuit generates first and second control pulses that become active at different timing during the active period of the first timing pulse, and

the third circuit is a sampling latch-type level shifter that is in a non-operating state during an active period of one of the first and second control pulses that is generated first and then takes the third timing pulse therein, and that is in an operating state when the control pulse is inactive, then latches the control pulse, and latches the latched data on a subsequent stage synchronously with the control pulse tat is generated later.

9. The display device as claimed in claim 7 wherein one of the third timing pulses is a pulse that is active during one horizontal scanning period in one field period.

10. The display device as claimed in claim 9 wherein the level converter circuit further comprises a fourth circuit that is in an operating state during an active period of the third timing pulse using the third timing pulse after the level conversion by the third circuit and performs level conversion of a fourth timing pulse from the first voltage amplitude to the second voltage amplitude.

11. The display device as claimed in claim 10 wherein the fourth circuit includes plural circuit parts corresponding to plural said fourth timing pulses.

12. The display device as claimed in claim 6, wherein display elements of the pixels are liquid crystal cells.

13. A display device comprising:

a pixel unit having pixels arrayed in a matrix on a board and having signal lines arranged for each row of the pixel array;

selection means provided on the same board as the pixel unit and adapted for time-divisionally selecting a set of plural signal lines and supplying a signal thereto; and

level conversion means for converting a selector pulse with a first voltage amplitude inputted from outside the board to a second voltage amplitude and supplying the converted selector pulse to the selection means, the level conversion means being inactive when the selection means is in a non-selection state and wherein the level conversion means has a first level shifter that becomes active in response to an enable pulse allowing supply of a signal to the signal lines and performs level shift of a first shift pulse, a second level shifter that becomes active at timing of vanishing of the first shift pulse level-shifted by the first level shifter and performs level shift of a second shift pulse, and a third level shifter that becomes active at timing of vanishing of the second shift pulse level-shifted by the second level shifter and performs level shift of a third shift pulse,

the first level shifter becoming inactive at timing of generation of the second shift pulse, the second level shifter becoming inactive at timing of generation of the third shift pulse, and the third level shifter becoming inactive at timing of vanishing of the enable pulse.

14. The display device as claimed in claim 13 wherein the level conversion means has an enable pulse level shifter that is constantly active, performs level shift of the enable pulse of the first voltage level inputted from outside of the board to the second voltage level and supplies the level-shifted enable pulse to the first level shifter.

15. A portable telephone device using, as an output display unit, a display device comprising a pixel unit having pixels arrayed in a matrix on a board, driving means provided on the same board as the pixel unit and adapted for driving the pixels of the pixel unit, and a level converter circuit for performing level conversion of a timing pulse of a first voltage amplitude inputted from outside the board to a second voltage amplitude and supplying the level-converted timing pulse to the driving means,

the level converter circuit comprising:

a first circuit that is constantly in an operating state and performs level conversion of a first timing pulse that becomes active during a horizontal blanking period of an image signal, from the first voltage amplitude to the second voltage amplitude; and

a second circuit that is in an operating state during an active period of the first timing pulse using the first timing pulse after the level conversion b the first circuit and performs level conversion of a second timing pulse from the first voltage amplitude to the second voltage amplitude, and wherein the level converter circuit further comprises;

a timing control circuit for generating a control pulse that becomes active during the active period of the first timing pulse on the basis of the first and second timing pulses after the level conversion by the first and second circuits; and

a third circuit that is in an operating state during an active period of the control pulse using the control pulse and performs level conversion of a third timing pulse from the first voltage amplitude to the second voltage amplitude.

16. The portable telephone device as claimed in claim 15, wherein the third circuit includes plural circuit parts corresponding to plural said third timing pulses.

17. The portable telephone device as claimed in claim 15, wherein the timing control circuit generates first and second control pulses that become active at different timing during the active period of the first timing pulse, and

the third circuit is a sampling latch-type level shifter that is in a non-operating state during an active period of one of the first and second control pulses that is generated first and then takes the third timing pulse therein, and that is in an operating state when the control pulse is inactive, then latches the control pulse, and latches the latched data on a subsequent stage synchronously with the control pulse that is generated later.

18. The portable telephone device as claimed in claim 16, wherein one of the third timing pulses is a pulse that is active during one horizontal scanning period in one field period.

19. The portable telephone device as claimed in claim 18, wherein the level converter circuit further comprises a fourth circuit that is in an operating state during an active period of the third timing pulse using the third timing pulse after the level conversion by the third circuit and performs level conversion of a fourth timing pulse from the first voltage amplitude to the second voltage amplitude.

20. The portable telephone device as claimed in claim 19, wherein the fourth circuit includes plural circuit parts corresponding to plural said fourth timing pulses.

21. The portable telephone device as claimed in claim 15, wherein the display device is a liquid crystal display device using liquid crystal cells as display elements of the pixels.

22. A portable telephone device having an output display unit and using a liquid crystal display device as the output display unit,

the liquid crystal display device comprising:

a pixel unit having pixels arrayed in a matrix on a board and having signal lines arranged for each row of the pixel array;

selection means provided on the same board as the pixel unit and adapted for time-divisionally selecting a set of plural signal lines and supplying a signal thereto; and

level conversion means for converting a selector pulse with a first voltage amplitude inputted from outside the board to a second voltage amplitude and supplying the converted selector pulse to the selection means, the level conversion means being inactive when the selection means is in a non-selection state and wherein the level conversion means has a first level shifter that becomes active in response to an enable pulse allowing supply of a signal to the signal lines and performs level shift of a first shift pulse, a second level shifter that becomes active at timing of vanishing of the first shift pulse level-shifted by the first level shifter and performs level shift of a second shift pulse, and a third level shifter that becomes active at timing of vanishing of the second shift pulse level-shifted by the second level shifter and performs level shift of a third shift pulse,

the first level shifter becoming inactive at timing of generation of the second shift pulse, the second level shifter becoming inactive at timing of generation of the third shift pulse, and the third level shifter becoming inactive at timing of vanishing of the enable pulse.

23. The portable telephone device as claimed in claim 22 wherein the level conversion means has an enable pulse level shifter that is constantly active, performs level shift of the enable pulse of the first voltage level inputted from outside of the board to the second voltage level and supplies the level-shifted enable pulse to the first level shifter.