API communications for vertex and pixel shaders

• US 7,116,332 B2
• Filed: 11/05/2004
• Issued: 10/03/2006
• Est. Priority Date: 03/07/2000
• Status: Expired due to Term

• Current Assignee: Microsoft Technology Licensing LLC (Microsoft Corporation)
• Original Assignee: Microsoft Corporation
• Inventors: Toelle, Michael A., Boyd, Charles F.
• Primary Examiner(s): Tung, Kee M.
• Assistant Examiner(s): NGUYEN, HAU H
• Application Number:
  US10/981,865
• Publication Number:
  US 20050280654A1
• Time in Patent Office: 697 Days
• Field of Search: 345/559, 345/426, 345/519, 345/552, 345/561, 345/537, 345/538, 345/643, 345/501, 345/502, 709/328
• US Class Current: 345/559
• CPC Class Codes: G06T 15/00 3D [Three Dimensional] image rendering
• CPC Class Codes: G06T 15/005 General purpose rendering architectures
• CPC Class Codes: G06T 15/80 Shading
• CPC Class Codes: G06T 2210/32 Image data format

Abstract

A three-dimensional API for communicating with hardware implementations of vertex shaders and pixel shaders having local registers. With respect to vertex shaders, API communications are provided that may make use of an on-chip register index and API communications are also provided for a specialized function, implemented on-chip at a register level, that outputs the fractional portion(s) of input(s). With respect to pixel shaders, API communications are provided for a specialized function, implemented on-chip at a register level, that performs a linear interpolation function and API communications are provided for specialized modifiers, also implemented on-chip at a register level, that perform modification functions including negating, complementing, remapping, stick biasing, scaling and saturating. Advantageously, these API communications expose these very useful on-chip graphical algorithmic elements to a developer while hiding the details of the operation of the vertex shader and pixel shader chips from the developer.

Claims

1. A computer-readable medium having computer-executable instructions communicating between a 3-D graphics API of a host computing system having a main memory stack and a hardware procedural shader having on-chip register storage, wherein the computer-executable instructions perform:

receiving at least one instruction having at least one graphics data argument by the 3-D API;

formatting said at least one instruction for use with the hardware procedural shader;

providing said at least one formatted instruction to said hardware procedural shader;

processing said at least one graphics data argument, pursuant to said at least one formatted instruction, by the hardware procedural shader without accessing the main memory stack of the host computing system;

outputting the result of said processed at least one graphics data argument from said hardware procedural shader in accordance with said at least one formatted instruction;

communicating between a 3-D graphics API of a host computing system and a hardware vertex shader with on-chip register storage, and said at least one instruction is an instruction with at least one floating point number argument and said outputting includes outputting from the vertex shader the fractional portion of said at least one floating point number; and

wherein said outputting includes outputting four fractional portions of corresponding four floating point number arguments.

2. The computer-readable medium of claim 1, wherein the computer-executable instructions further perform communicating said at least one instruction directly to said hardware procedural shader, thereby bypassing the main memory stack of the host computing system.

3. The computer-readable medium of claim 1, wherein said processing of said at least one graphics data argument includes performing at least one of reading from and writing to the on-chip register storage.

4. The computer-readable medium of claim 1, wherein the computer-executable instructions perform communicating between a 3-D graphics API of a host computing system and a hardware vertex shader with on-chip register storage, further comprising storing a register index in the on-chip register storage.

5. The computer-readable medium of claim 4, wherein the computer-executable instructions further perform accessing the register index stored in the on-chip register storage and finding another register of the register storage to be used incident to carrying out said at least one instruction by said hardware vertex shader.

6. The computer-readable medium of claim 1, wherein said hardware procedural shader includes a processor and an arithmetic/logic unit that aid in the performance of said processing.

7. The computer-readable medium of claim 1, wherein the computer-executable instructions perform communicating between a 3-D graphics API of a host computing system and a hardware pixel shader with on-chip register storage, and said at least one instruction is an instruction with a plurality of floating point number arguments and said processing includes processing the plurality of floating point number arguments to calculate a number representative of a linear interpolation between two of the floating point number arguments.

8. The computer-readable medium of claim 1, wherein the computer-executable instructions perform communicating between a 3-D graphics API of a host computing system and a hardware pixel shader with on-chip register storage, and said at least one instruction is an instruction with a plurality of floating point number arguments and said outputting includes outputting a floating point number representative of a linear interpolation between two of the floating point number arguments.

9. The computer-readable medium of claim 1, wherein the computer-executable instructions perform communicating between a 3-D graphics API of a host computing system and a hardware pixel shader with on-chip register storage, wherein said at least one instruction includes a special modifier function to be performed during said processing of the graphics data by the arithmetic/logic unit of the pixel shader.

10. The computer-readable medium of claim 9, wherein said special modifier function performed during said processing is at least one of a negating modifier, complementing modifier, remapping modifier, stick biasing modifier, saturating modifier and scaling modifier.

11. A system for communicating between a 3-D graphics API of a host computing system having a main memory stack and a hardware procedural shader having on-chip register storage, comprising:

a 3-D graphics API, wherein at least one instruction having at least one graphics data argument is received by the 3-D API;

a host computing system having a main memory stack;

a hardware procedural shader having on-chip register storage, wherein said at least one instruction is formatted and provided to the hardware procedural shader, and wherein said at least one graphics data argument is processed pursuant to said at least one formatted instruction by the hardware procedural shader without accessing the main memory stack of the host computing system;

an output for providing the result of said processed at least one graphics data argument from said hardware procedural shader in accordance with said at least one formatted instruction, wherein said outputting includes outputting four fractional portions of corresponding four floating point number arguments; and

a hardware vertex shader with on-chip register storage, wherein the 3-D graphics API of a host computing system and a hardware vertex shader communicates with the hardware vertex shader, and wherein said at least one instruction is an instruction with at least one floating point number argument and said outputting includes outputting from the vertex shader the fractional portion of said at least one floating point number.

12. The system of claim 11, wherein said at least one instruction communicates directly to said hardware procedural shader, thereby bypassing the main memory stack of the host computing system.

13. The system of claim 11, wherein said processing of said at least one graphics data argument includes performing at least one of reading from and writing to the on-chip register storage.

14. The system of claim 11, wherein said 3-D graphics API of a host computing system communicates with a hardware vertex shader with on-chip register storage, further comprising storing a register index in the on-chip register storage.

15. The system of claim 14, wherein said register index stored in the on-chip register storage is accessed to find another register of the register storage to be used incident to carrying out said at least one instruction by said hardware vertex shader.

16. The system of claim 11, wherein said hardware procedural shader includes a processor and an arithmetic/logic unit that aid in the performance of said processing.

17. The system of claim 11, wherein said 3-D graphics API of a host computing system communicates with a hardware pixel shader with on-chip register storage, and wherein said at least one instruction is an instruction with a plurality of floating point number arguments and said processing includes processing the plurality of floating point number arguments to calculate a number representative of a linear interpolation between two of the floating point number arguments.

18. The system of claim 11, wherein said 3-D graphics API of a host computing system communicates with a hardware pixel shader with on-chip register storage, and wherein said at least one instruction is an instruction with a plurality of floating point number arguments and said outputting includes outputting a floating point number representative of a linear interpolation between two of the floating point number arguments.

19. The system of claim 11, wherein said 3-D graphics API of a host computing system communicates with a hardware pixel shader with on-chip register storage, and wherein said at least one instruction includes a special modifier function to be performed during said processing of the graphics data by the arithmetic/logic unit of the pixel shader.

20. The system of claim 19, wherein said special modifier function performed during said processing is at least one of a negating modifier, complementing modifier, remapping modifier, stick biasing modifier, saturating modifier and scaling modifier.