Access circuit and method for allowing external test voltage to be applied to isolated wells

• US 7,116,570 B2
• Filed: 10/26/2005
• Issued: 10/03/2006
• Est. Priority Date: 12/29/2003
• Status: Expired due to Fees

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Zimlich, David A.
• Primary Examiner(s): Zarabian, Amir
• Assistant Examiner(s): PHAM, LY D
• Application Number:
  US11/259,841
• Publication Number:
  US 20060050570A1
• Time in Patent Office: 342 Days
• Field of Search: 365/72, 365/201, 365/175, 365/177, 257/499, 257/544
• US Class Current: 365/72
• CPC Class Codes: G11C 11/401 forming cells needing refreshing or charge regeneration, i.e. dynamic cells
• CPC Class Codes: G11C 29/12005 comprising voltage or current generators
• CPC Class Codes: G11C 29/1201 comprising I/O circuitry
• CPC Class Codes: G11C 29/48 Arrangements in static stores specially adapted for testing by means external to the store, e.g. using direct memory access [DMA] or using auxiliary access paths
• CPC Class Codes: G11C 29/50 Marginal testing, e.g. race, voltage or current testing
• CPC Class Codes: G11C 29/50016 of retention
• CPC Class Codes: G11C 5/066 Means for reducing external access-lines for a semiconductor memory clip, e.g. by multiplexing at least address and data signals
• CPC Class Codes: H01L 27/0222 Charge pumping, substrate bias generation structures
• CPC Class Codes: H10B 12/50 Peripheral circuit region structures

Abstract

An access circuit selectively couples an externally accessible terminal to each of a plurality of isolated DRAM wells in which respective DRAM arrays are fabricated. The access circuit for each well includes first and second transistors fabricated in respective wells coupled between the externally accessible terminal and a respective one of the DRAM wells. The well of the first transistor is coupled to the externally accessible terminal, and the well of the other transistor is coupled to a respective DRAM well. A control circuit applies select signals to gate electrodes of the first and second transistors. The control circuit includes respective shunt transistors that shunt the gate electrodes to the source regions of the first and second transistors when the transistors are turned off to isolate the respective DRAM wells from the external terminal regardless of the magnitude and polarity of a test voltage applied to the externally accessible terminal.

Claims

1. A memory device, comprising:

a row address circuit operable to receive and decode row address signals applied to external address terminals of the memory device;

a column address circuit operable to receive and decode column address signals applied to the external address terminals;

a plurality of memory cell arrays each operable to store data written to or read from the array at a location determined by the decoded row address signals and the decoded column address signals, each of the memory cell arrays being fabricated in a respective array well formed in a semiconductor substrate and isolated from each other;

a data path circuit operable to couple data signals corresponding to the data between each of the arrays and external data terminals of the memory device;

a command decoder operable to decode a plurality of command signals applied to respective external command terminals of the memory device, the command decoder being operable to generate control signals corresponding to the decoded command signals;

a plurality of access circuits each of which selectively couples a predetermined one of the external terminals to a respective one of the array wells, each of the access circuits comprising;

a first transistor fabricated in a first well formed in the semiconductor substrate that is isolated from the array wells, the first transistor having a first source-drain region fabricated in the first well and being coupled to the predetermined external terminal and to the first well, a second source-drain region fabricated in the first well, and a gate electrode fabricated between the first and second source-drain regions of the first transistor and coupled to receive a first select signal for the respective array well, the first transistor being fabricated in the first well in a manner that causes a first diode to be formed between the source and drain regions of the first transistor;

a second transistor fabricated in a second well formed in the semiconductor substrate that is isolated from the array wells, the second transistor having a first source-drain region fabricated in the second well and being coupled to the second source-drain region of the first transistor, a second source-drain region fabricated in the second well and being coupled to the second well and to a respective one of the array wells, and a gate electrode fabricated between the first and second source-drain regions of the second transistor and coupled to receive a second select signal for the respective array well, the second transistor being fabricated in the second well in a manner that causes a second diode to be formed between the source and drain regions of the second transistor, the second diode being coupled to the first diode in a back-to-back configuration;

a first control circuit for applying the first select signal to the gate electrode of the first transistor responsive to a first access signal; and

a second control circuit for applying the second select signal to the gate electrode of the second transistor responsive to a second access signal.

2. The memory device of claim 1 wherein each of the first and second control circuits comprise:

a shunt transistor having a gate terminal and a pair of source-drain terminals coupled between the predetermined external terminal and the gate electrode of a respective one of the first and second transistors; and

a control transistor having a gate terminal coupled to receive a respective one of the first and second access signals, the control transistor having a pair of source-drain terminals coupled between the predetermined external terminal and the gate terminal of the shunt transistor.

3. The memory device of claim 2 wherein each of the control circuits comprise a first switching transistor having a gate terminal coupled to receive the respective access signal, and a pair of source-drain terminals coupled between a supply voltage and the gate terminal of the control transistor.

4. The memory device of claim 3, further comprising a second switching transistor having a gate terminal coupled to receive a compliment of the respective access signal, and a pair of source-drain terminals coupled between the supply voltage and the gate terminal of the shunt transistor.

5. The memory device of claim 1 wherein the well in which the first transistor is fabricated is different from the well in which the second transistor is fabricated.

6. The memory device of claim 5 wherein the semiconductor substrate comprises an n-type substrate, and the wells in which the first and second transistors are fabricated and the array wells comprise respective p-type wells.

7. The memory device of claim 1 wherein each of the memory cell arrays fabricated in a respective one of the array wells comprise a dynamic random access memory cell array.

8. The memory device of claim 1 wherein the second control circuit is identical to the first control circuit.

9. A computer system, comprising:

a processor having a processor bus;

an input device coupled to the processor through the processor bus to allow data to be entered into the computer system;

an out put device coupled to the processor through the processor bus to allow data to be output from the computer system;

a data storage device coupled to the processor through the processor bus to allow data to be read from a mass storage device;

a memory controller coupled to the processor through the processor bus;

and a memory device coupled to the memory controller, the memory device comprising;

a row address circuit operable to receive and decode row address signals applied to external address terminal of the memory device;

a column address circuit operable to receive and decode column address signals applied to the external address terminal;

a plurality of memory cell arrays each operable to store data written to or read from the array at a location determined by the decoded row address signals and the decoded column address signals, each of the memory cell arrays being fabricated in a respective array well formed in a semiconductor substrate and isolated from each other;

a data path circuit operable to couple data signals corresponding to the data between each of the arrays and external data terminals of the memory device;

a command decoder operable to decode a plurality of command signals applied to respective external command terminals of the memory device, the command decoder being operable to generate control signals corresponding to the decoded command signals;

a plurality of access circuits each of which selectively couples a predetermined one of the external terminals to a respective one of the array wells, each of the access circuits comprising;

a first transistor fabricated in a first well formed in the semiconductor substrate that is isolated from the array wells, the first transistor having a first source-drain region fabricated in the first well and being coupled to the predetermined external terminal and to the first well, a second source-drain region fabricated in the first well, and a gate electrode fabricated between the first and second source-drain regions of the first transistor and coupled to receive a first select signal for the respective array well, the first transistor being fabricated in the first well in a manner that causes a first diode to be formed between the source and drain regions of the first transistor;

a second transistor fabricated in a second well formed in the semiconductor substrate that is isolated from the array wells, the second transistor having a first source-drain region fabricated in the second well and being coupled to the second source-drain region of the first transistor, a second source-drain region fabricated in the second well and being coupled to the second well and to a respective one of the array wells, and a gate electrode fabricated between the first and second source-drain regions of the second transistor and coupled to receive a second select signal for the respective array well, the second transistor being fabricated in the second well in a manner that causes a second diode to be formed between the source and drain regions of the second transistor, the second diode being coupled to the first diode in a back-to-back configuration;

a first control circuit for applying the first select signal to the gate electrode of the first transistor responsive to a first access signal; and

a second control circuit for applying the second select signal to the gate electrode of the second transistor responsive to a second access signal.

10. The computer system of claim 9 wherein each of the first and second control circuits comprise:

a shunt transistor having a gate terminal and a pair of source-drain terminals coupled between the predetermined external terminal and the gate electrode of a respective one of the first and second transistors; and

a control transistor having a gate terminal coupled to receive a respective one of the first and second access signals, the control transistor having a pair of source-drain terminals coupled between the predetermined external terminal and the gate terminal of the shunt transistor.

11. The computer system of claim 10 wherein each of the control circuits comprise a first switching transistor having a gate terminal coupled to receive the respective access signal, and a pair of source-drain terminals coupled between a supply voltage and the gate terminal of the control transistor.

12. The computer system of claim 11, further comprising a second switching transistor having a gate terminal coupled to receive a compliment of the respective access signal, and a pair of source-drain terminals coupled between a supply voltage and the gate terminal of the control transistor.

13. The computer system of claim 9 wherein the well in which the first transistor is fabricated is different from the well in which the second transistor is fabricated.

14. The computer system of claim 13 wherein the semiconductor substrate comprises an n-type substrate, and the first and second wells and the array wells comprise respective p-type wells.

15. The computer system of claim 9 wherein each of the memory arrays fabricated in a respective one of the array wells comprise a dynamic random access memory array.

16. The computer system of claim 9 wherein the second control circuit is identical to the first control circuit.