Memory organization in a switching device
First Claim
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1. An apparatus, comprising:
- a first input port configured to receive packets;
first and second output ports configured to output packets;
a memory having a plurality of memory addresses;
a first packet processor configured to divide packets received at the first input port into respective cells and store said cells in memory addresses of the memory;
a controller configured to select one of the first and second output ports to output respective packets stored as cells in memory addresses of the memory;
a second packet processor configured to assemble cells stored in memory addresses of the memory into respective packets and transmit the assembled packets to the respective ones of the first and second output ports selected by the controller.
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Abstract
A router for switching data packets from a source to a destination in a network in which the router includes a distributed memory. The distributed memory includes two or more memory banks. Each memory bank is used for storing uniform portions of a data packet received from a source and linking information for each data packet to allow for the extraction of the uniform portions of a data packet from distributed locations in memory in proper order after a routing determination has been made by the router.
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Citations
17 Claims
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1. An apparatus, comprising:
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a first input port configured to receive packets;
first and second output ports configured to output packets;
a memory having a plurality of memory addresses;
a first packet processor configured to divide packets received at the first input port into respective cells and store said cells in memory addresses of the memory;
a controller configured to select one of the first and second output ports to output respective packets stored as cells in memory addresses of the memory;
a second packet processor configured to assemble cells stored in memory addresses of the memory into respective packets and transmit the assembled packets to the respective ones of the first and second output ports selected by the controller. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8)
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9. An apparatus, comprising:
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a plurality of input ports, each configured to receive packets;
a plurality of output ports, each configured to output packets;
a first packet processor configured to generate a key for each packet received at the plurality of input ports based on a destination address contained in a header of the packet;
a memory for storing packets received at the plurality of input ports;
a second packet processor configured to perform a look-up operation on each key generated by the first packet processor to identify a respective output port for the packet corresponding to the key; and
a memory controller for retrieving packets stored in the memory for output at the respective output ports identified by the second packet processor. - View Dependent Claims (10, 11, 12)
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13. A packet processor comprising:
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a first input for receiving packets, each packet having a header comprising a destination address;
a key generation unit for generating a key for each received packet, each key comprising information relating to the destination address contained in the header of the respective packet;
a first output for outputting portions of the packets received at the first input; and
a second output for outputting keys generated by the key generation unit. - View Dependent Claims (14, 15, 16, 17)
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Specification