Method and apparatus for digital subscriber line access multiplexer stacking

• US 7,116,674 B2
• Filed: 01/16/2003
• Issued: 10/03/2006
• Est. Priority Date: 01/16/2003
• Status: Expired due to Term

• Current Assignee: UTStarcom Incorporated (UTStarcom Holdings Corp.)
• Original Assignee: UTStarcom Incorporated (UTStarcom Holdings Corp.)
• Inventors: Shi, Qun
• Primary Examiner(s): Pham, Chi
• Assistant Examiner(s): Philpott, Justin M.
• Application Number:
  US10/346,485
• Publication Number:
  US 20040141609A1
• Time in Patent Office: 1,356 Days
• Field of Search: 370419-421, 709/250
• US Class Current: 370/419
• CPC Class Codes: H04L 12/5601 Transfer mode dependent, e.g. ATM
• CPC Class Codes: H04L 12/6418 Hybrid transport
• CPC Class Codes: H04L 2012/5606 Metallic
• CPC Class Codes: H04L 2012/561 Star, e.g. cross-connect, concentrator, subscriber group equipment, remote electronics
• CPC Class Codes: H04L 2012/5627 Fault tolerance and recovery
• CPC Class Codes: H04L 2012/5665 Interaction of ATM with other protocols
• CPC Class Codes: H04L 2012/6427 Subscriber Access Module; Concentrator; Group equipment
• CPC Class Codes: H04L 2012/6478 Digital subscriber line, e.g. DSL, ADSL, HDSL, XDSL, VDSL
• CPC Class Codes: H04M 11/062 using different frequency bands for speech and other data
• CPC Class Codes: H04Q 2213/13039 Asymmetrical two-way transmission, e.g. ADSL, HDSL
• CPC Class Codes: H04Q 2213/1305 Software aspects
• CPC Class Codes: H04Q 2213/13109 Initializing, personal profile
• CPC Class Codes: H04Q 2213/13145 Rerouting upon failure
• CPC Class Codes: H04Q 2213/13164 Traffic (registration, measurement,...)
• CPC Class Codes: H04Q 2213/13166 Fault prevention
• CPC Class Codes: H04Q 2213/13167 Redundant apparatus
• CPC Class Codes: H04Q 2213/13204 Protocols
• CPC Class Codes: H04Q 2213/1329 Asynchronous transfer mode, ATM
• CPC Class Codes: H04Q 2213/13298 Local loop systems, access network

Abstract

An architecture for stacking DSLAMs employs a master DSLAM having a control circuit and an uplink communication circuit to a central office and two LVDS circuits for communication with two DSLAM boxes in adjacent circuit interconnection to the master DSLAM. Multiple slave DSLAMs each having a programmable control circuit and two LVDS circuits for communication with two DSLAM boxes immediately adjacent on either side in the circuit are connected in a ring or split stack arrangement. A control circuit in the master selectively programs the control circuits in each slave DSLAM to control the direction of communication in the LVDS circuits as round robin in a first selected mode and a split in a second selected mode to accommodate the desired structure.

Claims

1. An architecture for stacking Digital Subscriber Line Access Multiplexers (DSLAMs) comprising:

a single master DSLAM having a control circuit and an uplink communication circuit to a central office and two low voltage differential signaling (LVDS) circuits for communication with two DSLAM boxes in direct adjacent circuit interconnection to the single master DSLAM;

a plurality of slave DSLAMs each having a programmable control circuit and two LVDS circuits for communication with two DSLAM boxes in adjacent virtual circuit interconnection; and

means for selectively programming the control circuits in each slave DSLAM to control the direction of communication in the LVDS circuits in said each slave DSLAM as round robin in a first selected mode and a split in a second selected mode, said split selectively programmed at a desired virtual circuit connection adjacent to the single master DSLAM for communication only through that single master DSLAM.

2. An architecture for stacking DSLAMs as defined in claim 1 wherein the two DSLAM boxes in adjacent circuit connection to the single master DSLAM are a first and a last slave DSLAMs to form a ring structure.

3. An architecture for stacking DSLAMs as defined in claim 1 wherein the two DSLAM boxes in direct adjacent circuit connection to the master are a first and a middle slave DSLAMs to form a dual link structure.

4. An architecture for stacking DSLAMs as defined in claim 1 wherein the means for selectively programming the slave DSLAMs employs a proxy scheme for data and management messages, based on virtual box identification and virtual path/circuit identifications.

5. An architecture for stacking DSLAMs as defined in claim 1 wherein the means for selectively programming the slave DSLAMs employs a relaying traffic mechanism for data and management messages, based on virtual box identification and virtual path/circuit identifications.

6. An architecture for stacking DSLAMs as defined in claim 1 further comprising means for detecting failure of one of the slave DSLAMs and wherein the means for selectively programming is responsive to the means for detecting failure to allow reprogramming from a round robin to split path communication around the failed slave DSLAM while retaining communication only through the single master DSLAM.

7. An architecture for stacking DSLAMs as defined in claim 6 further comprising a standby master wherein upon failure of the single master DSLAM, the standby master is enabled for operation as a single master having a control circuit and an uplink communication circuit to a central office and two low voltage differential signaling (LVDS) circuits for communication with two DSLAM boxes in direct adjacent circuit interconnection to the single master DSLAM and said means for selectively programming reprograms from a round robin to split path communication around the failed single master DSLAM while retaining communication through the standby master as a new single master DSLAM said split selectively programmed at a desired virtual circuit connection adjacent to the standby master for communication through the standby master.

8. An architecture for stacking Digital Subscriber Line Access Multiplexers (DSLAMs) comprising:

a single master DSLAM having a control circuit and an uplink communication circuit to a central office and two low voltage differential signaling (LVDS) circuits for communication with two DSLAM boxes in direct adjacent circuit interconnection to the single master DSLAM;

a plurality of slave DSLAMs each having a programmable control circuit and two LVDS circuits for communication with two DSLAM boxes in adjacent virtual circuit interconnection; and

means for selectively programming the control circuits in each slave DSLAM to control the direction of communication in the LVDS circuits in said each slave DSLAM as round robin in a first selected mode and a split in a second selected mode, said split selectively programmed at a desired virtual circuit connection adjacent to the single master for communication through that single master DSLAM;

means for detecting failure of one of the slave DSLAMs and wherein the means for selectively programming is responsive to the means for detecting failure to allow reprogramming from a round robin to split path communication around the failed slave DSLAM while retaining communication through the single master DSLAM; and

a standby master wherein upon failure of the single master, the standby master is enabled for operation as a single master having a control circuit and an uplink communication circuit to a central office and two low voltage differential signaling (LVDS) circuits for communication with two DSLAM boxes in direct adjacent circuit interconnection to the single master DSLAM, and said means for selectively programming reprograms from a round robin to split path communication around the failed single master DSLAM while retaining communication through the standby master as a new single master DSLAM, said split selectively programmed at a desired virtual circuit connection adjacent to the standby master for communication through the standby master.