Digital decimation filter having finite impulse response (FIR) decimation stages

• US 7,117,235 B2
• Filed: 11/06/2002
• Issued: 10/03/2006
• Est. Priority Date: 11/06/2002
• Status: Expired due to Fees

• Current Assignee: Comtech EF Data (Comtech Telecommunications Corporation)
• Original Assignee: Comtech EF Data (Comtech Telecommunications Corporation)
• Inventors: Cannon, Richard Hollingsworth
• Primary Examiner(s): Mai, Tan V.
• Application Number:
  US10/289,485
• Publication Number:
  US 20040088343A1
• Time in Patent Office: 1,427 Days
• Field of Search: 708/313
• US Class Current: 708/313
• CPC Class Codes: H03H 17/0288 Recursive, non-recursive, ladder, lattice structures
• CPC Class Codes: H03H 17/0664 where the output-delivery frequency is lower than the input sampling frequency, i.e. decimation
• CPC Class Codes: H03H 17/0671 Cascaded integrator-comb [CIC] filters

Abstract

A digital decimation filter having Finite Impulse Response (FIR) decimation stages provides improved performance over a Hogenauer decimating filter. The filter comprises multiple integrator stages followed by multiple FIR decimating stages. The zeros of the filter are tunable by adjusting the integer coefficients of the FIR stages providing tunability of the cut-off response, as opposed to the fixed sinc response of the Hogenauer filter. As a result, the number of required stages for a particular steepness is reduced, dramatically reducing the amount of digital circuitry required to implement a particular filter design. The improved filter is especially suitable for use in digital intermediate frequency (IF) stages in receivers, and for code-based applications where selectable decimation rate is desired and a fast multiply is not available.

Claims

1. A digital filter circuit, comprising:

a plurality of cascaded integrator stages coupled to an input of said digital filter circuit; and

a plurality of cascaded finite impulse response (FIR) filter stages, wherein a first one of said FIR filter stages has an input coupled to an output of a last one of said integrator stages, wherein a transfer function from said input of said digital filter circuit to an output of a last one of said FIR filter stages has a finite DC gain and a frequency domain shaping characteristic, and wherein said last FIR filter stages is decimated substantially with respect to said output of said last integrator.

2. The digital filter circuit of claim 1, further comprising a plurality of decimate-by-two blocks, each disposed between a pair of said plurality FIR stages, whereby each of said plurality of FIR filter stages operates at a rate decimated by two with respect to a preceding one of said plurality of FIR filter stages, excepting a first one of said plurality of FIR filter stages.

3. The digital filter circuit of claim 1, wherein said FIR filter stages are transformed stages having tap coefficients determined by differences between pairs of sequential coefficients of the Z-transform of a predetermined FIR filter stage transfer function, whereby said FIR filter stages are transformed to operate on an integrated signal to produce said FIR filter stage transfer function.

4. The digital filter circuit of claim 3, wherein each of said FIR filter stages includes a number of delay elements coupled in sequence equal to the order of said FIR filter stage transfer function plus one.

5. The digital filter circuit of claim 1, further comprising a decimation block having a decimation factor equal to the overall desired decimation factor of said plurality of FIR filter stages divided by two raised to a power equal to a quantity of said plurality of FIR filter stages.

6. The digital filter circuit of claim 5, further comprising a plurality of decimate-by-two blocks, each disposed between a pair of said plurality FIR stages, whereby each of said plurality of FIR filter stages operates at a rate decimated by two with respect to a preceding one of said plurality of FIR filter stages, excepting a first one of said plurality of FIR filter stages.

7. The digital filter circuit of claim 6, wherein said FIR filter stages are transformed stages having tap coefficients determined by differences between pairs of sequential coefficients of the Z-transform of a predetermined FIR filter stage transfer function, whereby said FIR filter stages are transformed to operate on an integrated signal to produce said FIR filter stage transfer function, and wherein each of said FIR filter stages includes a number of delay elements coupled in sequence equal to the order of said FIR filter stage transfer function plus one.

8. The digital filter circuit of claim 7, further comprising an equalizer filter having a frequency response substantially equal to an inverse of a Nyquist passband droop of said plurality of FIR filter sections.

9. The digital filter circuit of claim 1, further comprising an equalizer filter having a frequency response substantially equal to an inverse of a Nyquist passband droop of said plurality of FIR filter sections.

10. A digital filter circuit, comprising:

a plurality of cascaded integrator stages coupled to an input of said digital filter circuit; and

filter means having a predetermined order for providing decimation and a stopband having a rate of gain reduction greater than that of a sinc transfer function of equivalent order to said predetermined order.

11. The digital filter circuit of claim 10, further comprising decimation adjusting means for adjusting a decimation factor of said digital filter circuit to set an output rate of said digital filter circuit.

12. The digital filter circuit of claim 11, wherein said a bandwidth of said digital filter circuit is adjustable and wherein said adjusting means scales said decimation factor in conformity with adjustment of said bandwidth.

13. A method for processing a signal in the digital domain, comprising:

integrating said signal by a predetermined integration order;

filtering said signal through a plurality of finite impulse response (FIR) filter stages to produce a result consistent with a finite DC gain and a frequency domain shaping characteristic, and wherein filtering further decimates substantially a result of said integrating.

14. The method of claim 13, wherein said filtering is performed by processing said signal through sets of cascaded delays, each set of cascaded delays having feed-forward taps for providing a portion of said FIR filter stage frequency domain shaping characteristic, and wherein coefficients of said taps are determined by differences between pairs of sequential coefficients of the Z-transform of said FIR filter stage frequency domain shaping characteristic.

15. The method of claim 13, further comprising scaling said result of said integrating by a factor equal to the decimation factor of said plurality of FIR filter stages divided by two raised to a power equal to a quantity of said plurality of FIR filter stages, and wherein said filtering filters a result of said scaling.

16. A digital signal processing system, comprising:

a memory for storing program instructions and data; and

a processor coupled to said memory for executing said program instructions, wherein said program instructions comprise program instructions for

integrating said signal by a predetermined integration order,

decimating substantially a result of said integrating, and

filtering said signal by programmatic implementation of a plurality of finite impulse response (FIR) filter stages to produce a resulting consistent with a finite DC gain and a frequency domain shaping characteristic.

17. The digital signal processing system of claim 16, wherein said program instructions for filtering comprise program instructions for generating sets of cascaded delays, each set of cascaded delays having feedforward taps for providing a portion of said FIR filter stage frequency domain shaping characteristic, and wherein coefficients of said taps are determined by differences between pairs of sequential coefficients of the Z-transform of said FIR filter stage frequency domain shaping characteristic.

18. The digital signal processing system method of claim 17, further comprising program instructions for scaling said result of said integrating by a factor equal to the decimation factor of said plurality of FIR filter stages divided by two raised to a power equal to a quantity of said plurality of FIR filter stages, and wherein said program instructions for filtering filter a result of said scaling.