Hypertransport data path protocol

• US 7,117,308 B1
• Filed: 04/06/2004
• Issued: 10/03/2006
• Est. Priority Date: 04/06/2004
• Status: Active Grant

• Current Assignee: Cisco Technology, Inc. (Cisco Systems, Inc.)
• Original Assignee: Cisco Technology, Inc. (Cisco Systems, Inc.)
• Inventors: Scott, Jeffery B., Barach, David Richard, Potter, Kenneth H. Jr., Mitten, John W., Hoult, Kent, Riedle, Christopher G.
• Primary Examiner(s): Elmore, Reba I.
• Application Number:
  US10/818,670
• Time in Patent Office: 910 Days
• Field of Search: 711/118, 711/144, 711/156, 710/112
• US Class Current: 711/118
• CPC Class Codes: G06F 13/387 for adaptation of different data processing systems to different peripheral devices, e.g. protocol converters for incompatible systems, open system

Abstract

A data path protocol eliminates most of the conventional read transactions required to transfer data between devices interconnected by a split transaction bus, such as a HyperTransport (HPT) bus. To that end, each device is configured to manage its own set of buffer descriptors, unlike previous data path protocols in which only one device managed all the buffer descriptors. As such, neither device has to perform a read transaction to retrieve a “free” buffer descriptor from the other device. As a result, only write transactions are performed for transferring descriptors across the HPT bus, thereby decreasing the amount of traffic over the bus and eliminating conventional latencies associated with read transactions. In addition, because descriptors are separately managed in each device, the data path protocol also conserves processing bandwidth that is traditionally consumed by managing ownership of the buffer descriptors within a single device.

Claims

1. A method for transferring data between a first device and a second device interconnected by a bus, the method comprising:

receiving the data at the first device;

retrieving, by the first device, a first buffer descriptor from a pool of free buffer descriptors, without having to perform a read transaction over the bus;

storing the data in a first data buffer referenced by the first buffer descriptor; and

transferring the first buffer descriptor over the bus from the first device to the second device.

2. The method of claim 1, further comprising:

processing the data at the second device;

storing the processed data in a second data buffer referenced by a second buffer descriptor;

transferring the second buffer descriptor from the second device to the first device, without having to perform a read transaction over the bus;

retrieving, by the first device, the processed data from the second data buffer; and

storing the second buffer descriptor in the pool of free buffer descriptors.

3. The method of claim 2, wherein if a predetermined condition is satisfied, the second buffer descriptor is returned to the second device instead of being stored in the pool of free buffer descriptors.

4. The method of claim 2, wherein the first and second data buffers are the same data buffer.

5. The method of claim 2, wherein the first and second data buffers are located in the second device.

6. The method of claim 2, further comprising:

incorporating software data into at least one of the first and second buffer descriptors.

7. The method of claim 1, wherein the step of transferring the first buffer descriptor over the bus from the first device to the second device further comprises:

storing the first buffer descriptor in a CPU cache in the second device.

8. The method of claim 2, further comprising:

performing flow control operations when transferring at least one of the first and second buffer descriptors between the first and second devices.

9. The method of claim 2, further comprising:

transmitting to the first device a requested number of buffer descriptors to be transferred from the second device to the first device; and

notifying, by the first device, the second device when the requested number of buffer descriptors can be forwarded to the first device.

10. The method of claim 1, wherein the bus is a split transaction bus.

11. A method for transferring processed data from a second device to a first device interconnected by a bus, the method comprising:

processing the data at the second device;

storing the processed data in a data buffer referenced by a buffer descriptor;

transferring the buffer descriptor from the second device to the first device, without having to perform a read transaction over the bus;

retrieving, by the first device, the processed data from the data buffer; and

storing the buffer descriptor in a pool of free buffer descriptors available to the first device.

12. An apparatus for transferring data between a first device and a second device interconnected by a bus, the apparatus comprising:

means for receiving the data at the first device;

means for retrieving, by the first device, a first buffer descriptor from a pool of free buffer descriptors, without having to perform a read transaction over the bus;

means for storing the data in a first data buffer referenced by the first buffer descriptor; and

means for transferring the first buffer descriptor over the bus from the first device to the second device.

13. An apparatus for transferring processed data from a second device to a first device interconnected by a bus, the apparatus comprising:

means for processing the data at the second device;

means for storing the processed data in a data buffer referenced by a buffer descriptor;

means for transferring the buffer descriptor from the second device to the first device, without having to perform a read transaction over the bus;

means for retrieving, by the first device, the processed data from the data buffer; and

means for storing the buffer descriptor in a pool of free buffer descriptors available to the first device.

14. A computer-readable media including instructions for execution by a processor, the instructions for a method of transferring data between a first device and a second device interconnected by a bus, the method comprising:

receiving the data at the first device;

retrieving, by the first device, a first buffer descriptor from a pool of free buffer descriptors, without having to perform a read transaction over the bus;

storing the data in a first data buffer referenced by the first buffer descriptor; and

transferring the first buffer descriptor over the bus from the first device to the second device.

15. A computer-readable media including instructions for execution by a processor, the instructions for a method of transferring processed data from a second device to a first device interconnected by a bus, the method comprising:

processing the data at the second device;

storing the processed data in a data buffer referenced by a buffer descriptor;

transferring the buffer descriptor from the second device to the first device, without having to perform a read transaction over the bus;

retrieving, by the first device, the processed data from the data buffer; and

storing the buffer descriptor in a pool of free buffer descriptors available to the first device.

16. A system configured to transfer data between devices interconnected by a bus, the system comprising:

a first device including;

a central processing unit (CPU) adapted to execute software code that instructs the CPU how to process the data, and

a memory having a plurality of memory locations addressable by the CPU, the memory adapted to store (i) a buffer cache containing one or more data buffers in which the data can be stored and (ii) a To-CPU descriptor ring configured to store one or more buffer descriptors referencing data buffers in the buffer cache; and

a second device coupled to the first device over the bus, the second device including;

a To-CPU data FIFO configured to store the data when the data is received at the second device,

a free buffer cache configured to store a pool of free buffer descriptors, each free buffer descriptor referencing a memory location of a corresponding data buffer in the first device'"'"'s buffer cache, wherein each data buffer referenced by a free buffer descriptor is available to store at least a portion of the data stored in the To-CPU data FIFO, and

a To-CPU direct memory access (DMA) engine configured to (i) acquire a free buffer descriptor from the pool of free buffer descriptors without performing a read transaction over the bus, (ii) transfer the data from the To-CPU data FIFO, over the bus, to the data buffer referenced by the acquired free buffer descriptor, (iii) enqueue the acquired descriptor at an appropriate location in the To-CPU descriptor ring and (iv) notify the CPU that the data has been transferred to the first device.

17. The system of claim 16, wherein the To-CPU data FIFO comprises a data section configured to store the data and further comprises at least one of:

a start-of-packet value that indicates whether the data contains the start of a data packet received at the second device;

an end-of-packet value that indicates whether the data contains the end of a data packet received at the second device;

an error value that indicates whether an error has been detected in the data; and

a ring-select value that identifies a destination for the data.

18. The system of claim 16, wherein the To-CPU DMA engine is configured to modify the acquired descriptor before enqueueing the acquired descriptor in the To-CPU descriptor ring.

19. The system of claim 18, wherein the acquired descriptor is modified by adding software data or packet header data to the contents of the descriptor.

20. The system of claim 16, wherein the second device further comprises a general configuration register configured to store at least one of:

a ring-enable value that indicates whether the second device is permitted to enqueue the acquired descriptor in the To-CPU descriptor ring;

a transfer-mode value that indicates whether the To-CPU DMA engine is permitted to transfer the data from the To-CPU data FIFO to the data buffer referenced by the acquired descriptor;

a flow-control value that indicates whether a flow-control mechanism is used to control the rate data is transferred out of the To-CPU data FIFO;

a cache-coherency value that indicates whether the To-CPU DMA engine is permitted to store descriptors in a CPU cache accessible to the CPU; and

a byte-swap value that indicates whether the To-CPU DMA engine should byte swap the data before transferring the data to the data buffer referenced by the acquired descriptor.

21. The system of claim 16, wherein the second device further comprises:

a From-CPU data FIFO configured to store data processed by the CPU;

a From-CPU descriptor FIFO configured to store one or more buffer descriptors referencing data buffers containing data processed by the CPU; and

a From-CPU DMA engine configured to (i) dequeue a buffer descriptor from the From-CPU descriptor FIFO without first receiving a read transaction over the bus, (ii) transfer the data referenced by the dequeued descriptor from its containing data buffer, over the bus, to the From-CPU data FIFO and (iii) store the dequeued descriptor in the pool of free buffer descriptors if a predetermined condition is satisfied.

22. The system of claim 21, wherein the CPU stores a replica of the From-CPU descriptor FIFO in the memory of the first device.

23. The system of claim 21, wherein the predetermined condition is satisfied when the CPU does not request that the dequeued descriptor be returned to the first device.

24. The system of claim 23, wherein a reuse-buffer enable value stored in the dequeued descriptor indicates whether the CPU requests that the dequeued descriptor be returned to the first device.

25. The system of claim 23, wherein if the predetermined condition is not satisfied, the dequeued descriptor is returned to the first device.

26. The system of claim 21, wherein the CPU enqueues descriptors into the From-CPU descriptor FIFO.

27. The system of claim 26, wherein prior to enqueueing descriptors into the From-CPU descriptor FIFO, the CPU sends a request for a predetermined number of available entries in the From-CPU descriptor FIFO.

28. The system of claim 21, wherein the second device further comprises a general configuration register configured to store at least one of:

a FIFO-enable value that indicates whether the CPU is permitted to enqueue a descriptor into the From-CPU descriptor ring;

an arbitration-mode value that indicates an amount of descriptors that can be dequeued from the From-CPU descriptor FIFO by the From-CPU DMA engine;

a flow-control value that indicates whether a flow-control mechanism is used to control the rate that data is transferred into the From-CPU data FIFO;

a byte-swap value that indicates whether the From-CPU DMA engine should byte swap data before the data is stored in the From-CPU data FIFO.