Memory hub and access method having internal row caching

• US 7,117,316 B2
• Filed: 08/05/2002
• Issued: 10/03/2006
• Est. Priority Date: 08/05/2002
• Status: Active Grant

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Jeddeloh, Joseph M.
• Primary Examiner(s): KIM, HONG CHONG
• Application Number:
  US10/213,038
• Publication Number:
  US 20040024978A1
• Time in Patent Office: 1,520 Days
• Field of Search: 711/154, 711/118, 711/105, 711/109, 709/214, 345/557
• US Class Current: 711/154
• CPC Class Codes: G06F 12/0862 with prefetch
• CPC Class Codes: G06F 12/0893 Caches characterised by their organisation or structure
• CPC Class Codes: G06F 13/161 with latency improvement

Abstract

A computer system includes a controller coupled to a plurality of memory modules each of which includes a memory hub and a plurality of memory devices. The memory hub includes a row cache memory that stores data as they are read from the memory devices. When the memory module is not being accessed by the controller, a sequencer in the memory module generates requests to read data from a row of memory cells. The data read responsive to the generated read requests are also stored in the row cache memory. As a result, read data in the row being accessed may be stored in the row cache memory even though the data was not previously read from the memory device responsive to a memory request from the controller.

Claims

1. A computer system, comprising:

a central processing unit (“

CPU”

);

a system controller coupled to the CPU, the system controller having an input port and an output port;

an input device coupled to the CPU through the system controller;

an output device coupled to the CPU through the system controller;

a storage device coupled to the CPU through the system controller;

a plurality of memory modules, each of the memory modules comprising;

a plurality of memory devices; and

a memory hub, comprising;

a link interface having an input port and an output port, the link interface receiving memory requests through the input port for access to a row of memory cells in at least one of the memory devices and outputting data through the output port responsive to the memory requests;

a memory device interface coupled to the memory devices, the memory device interface being operable to couple memory requests to the memory devices for access to a row of memory cells in at least one of the memory devices and to receive read data responsive to at least some of the memory requests, at least some of the memory requests coupled to the memory devices being responsive to memory requests transferred from the link interface to the memory device interface;

a row cache memory coupled to the memory device interface for receiving and storing read data from a row of memory cells being accessed responsive to at least one of the memory requests being coupled from the memory device interface to the at least one memory device; and

a sequencer coupled to the link interface and the memory device interface and the row cache memory, the sequencer being operable to generate and couple to the memory device interface memory requests to read data from memory cells in row of memory cells being accessed, the read data read from the memory cells in the row of memory cells being accessed being stored in the row cache memory; and

a communications link coupling the output port of the system controller to the input port of the memory hub in each of the memory modules, and coupling the input port of the system controller to the output port of the memory hub in each of the memory modules.

2. The computer system of claim 1 wherein the memory device interface further comprises a first-in, first-out buffer that is operable to receive and to store memory requests received from the link interface and from the sequencer and to transfer the stored memory requests to the at least one memory device in the order in which they were received.

3. The computer system of claim 1 wherein the link interface comprises a first-in, first-out buffer that is operable to receive and store memory requests and to transfer the stored memory requests to the memory device interface in the order in which they were received.

4. The computer system of claim 3 wherein the memory device interface further comprises a first-in, first-out buffer that is operable to receive and store memory requests received from the link interface and from the sequencer and to transfer the stored memory requests to the at least one memory device in the order in which they were received.

5. The computer system of claim 1 wherein the memory devices comprises dynamic random access memory devices.

6. The computer system of claim 1 wherein the sequencer is operable to output an address contained in each read memory request received from the link interface, and wherein the row cache memory is operable to receive the addresses from the sequencer to determine if data called for by the memory request is stored in the row cache memory, the row cache memory outputting the read data and generating a hit signal if the data called for by the memory request is stored in the row cache memory and generating a row miss signal if the data called for by the memory request is not stored in the row cache memory.

7. The computer system of claim 6 further comprising a multiplexer having data inputs coupled to the row cache memory and to the memory device interface, a data output coupled to the link interface and a control input coupled to receive the row cache hit and row cache miss signals from the row cache memory, the multiplexer coupling read data from the memory device interface responsive to the row cache miss signal and coupling read data from the row cache memory responsive to the row cache hit signal.

8. The computer system of claim 1 wherein the sequencer is operable to generate and couple to the memory device interface memory requests to read data from memory cells in row of memory cells being accessed only when memory requests are not being transferred from the link interface to the memory device interface.

9. The computer system of claim 1 wherein the input and output ports of the system controller comprises a combined input/output port coupled to the communications link, and wherein the input and output ports of each of the memory hubs comprises a combined input/output port coupled to the communications link.

10. The computer system of claim 9 wherein the communications link comprises optical communications link, wherein the input and output ports of the system controller comprises an optical input/output port coupled to the optical communications link and wherein the input and output ports of each of the memory hubs comprises a respective optical input/output port coupled to the optical communications link.

11. A computer system, comprising:

a central processing unit (“

CPU”

);

a system controller coupled to the CPU, the system controller having an input port and an output port;

an input device coupled to the CPU through the system controller;

an output device coupled to the CPU through the system controller;

a storage device coupled to the CPU through the system controller;

a plurality of memory modules, each of the memory modules comprising;

a plurality of memory devices; and

a memory hub, comprising;

a link interface receiving memory requests for access to a row of memory cells in at least one of the memory devices;

a memory device interface coupled to the memory devices, the memory device interface being operable to couple memory requests to the memory devices for access to a row of memory cells in at least one of the memory devices and to receive read data responsive to at least some of the memory requests, at least some of the memory requests coupled to the memory devices being responsive to memory requests transferred from the link interface to the memory device interface;

a sequencer coupled to the link interface and the memory device interface and the row cache memory, the sequencer being operable to output an address contained in each read memory request received from the link interface;

a row cache memory coupled to the memory device interface for receiving and storing read data from a row of memory cells being accessed responsive to one of the memory requests being coupled from the memory device interface to the at least one memory device, the row cache memory further being operable to receive the addresses from the sequencer to determine if data called for by the memory request is stored in the row cache memory, the row cache memory outputting the read data and generating a hit signal if the data called for by the memory request is stored in the row cache memory and generating a row miss signal if the data called for by the memory request is not stored in the row cache memory; and

a multiplexer having data inputs coupled to the row cache memory and to the memory device interface;

a data output coupled to the link interface and a control input coupled to receive the row cache hit and row cache miss signals from the row cache memory, the multiplexer coupling read data from the memory device interface responsive to the row cache miss signal and coupling read data from the row cache memory responsive to the row cache hit signal; and

a communications link coupling the output port of the system controller to the input port of the memory hub in each of the memory modules, and coupling the input port of the system controller to the output port of the memory hub in each of the memory modules.

12. The computer system of claim 11 wherein the memory device interface farther comprises a first-in, first-out buffer that is operable to receive and store memory requests received from the link interface and from the sequencer and to transfer the stored memory requests to the at least one memory device in the order in which they were received.

13. The computer system of claim 11 wherein the link interface comprises a first-in, first-out buffer that is operable to receive and store memory requests and to transfer the stored memory requests to the memory device interface in the order in which they were received.

14. The computer system of claim 13 wherein the memory device interface further comprises a first-in, first-out buffer that is operable to receive and store memory requests received from the link interface and from the sequencer and to transfer the stored memory requests to the at least one memory device in the order in which they were received.

15. The computer system of claim 11 wherein the link interface comprises an optical input/output port.

16. The computer system of claim 11 wherein the memory devices comprises dynamic random access memory devices.

17. The computer system of claim 11 wherein the input and output ports of the system controller comprises a combined input/output port coupled to the communications link, and wherein the input and output ports of each of the memory hubs comprises a combined input/output port coupled to the communications link.

18. The computer system of claim 17 wherein the communications link comprises an optical communications link, wherein the input and output ports of the system controller comprises an optical input/output port coupled to the optical communications link and wherein the input and output ports of each of the memory hubs comprises a respective optical input/output port coupled to the optical communications link.