Debug port disable mechanism

• US 7,117,352 B1
• Filed: 12/20/2002
• Issued: 10/03/2006
• Est. Priority Date: 02/13/2002
• Status: Expired due to Fees

• Current Assignee: Avago Technologies General IP PTE Limited (Broadcom, Inc.)
• Original Assignee: LSI Logic Corporation (Broadcom, Inc.)
• Inventors: Giles, Christopher M., Bewick, Simon, Williams, Kalvin E.
• Primary Examiner(s): Moise, Emmanuel L.
• Assistant Examiner(s): ABYANEH, ALI S
• Application Number:
  US10/325,192
• Time in Patent Office: 1,383 Days
• Field of Search: 713/2
• US Class Current: 713/2
• CPC Class Codes: G01R 31/31705 Debugging aspects, e.g. using test circuits for debugging, using dedicated debugging test circuits generation of test sequences therefor G01R31/31835, using scan test therefor G01R31/318544
• CPC Class Codes: G01R 31/31719 Security aspects, e.g. preventing unauthorised access during test
• CPC Class Codes: G01R 31/318533 using scanning techniques, e.g. LSSD, Boundary Scan, JTAG

Abstract

A circuit generally comprising a debug port and a processor is disclosed. The processor may be configured to (i) bootstrap to a first memory, (ii) disable said debug port while in a first mode of at least three modes, (iii) authenticate said debug port while in a second mode of said modes and (iv) disable said debug port in response to failing said authentication.

Claims

1. A circuit comprising:

a debug port; and

a processor configured to (i) bootstrap to a first memory while in a highest mode of security, (ii) disable said debug port while in said highest mode of security, (iii) authenticate said debug port, (iv) disable said debug port before transitioning to an intermediate mode of security in response to failing said authentication and (v) enable said debug port while in a lowest mode of said security.

2. The circuit according to claim 1, further comprising:

an enable module configured to mask an input signal generated external to said circuit and receivable by said debug port in response to disabling said debug port.

3. The circuit according to claim 1, further comprising:

a security circuit configured to enable said debug port.

4. The circuit according to claim 1, wherein said first memory stores a debug exception vector configured to jump to self in response to a debug exception.

5. The circuit according to claim 1, wherein a debug flag determines if access to a debug exception vector is allowed in response to a debug exception.

6. The circuit according to claim 1, wherein operation in said highest mode of security, said intermediate mode of security and said lowest mode of security is determined by a multiple-bit value stored in a register as greater than two bits.

7. The circuit according to claim 6, wherein said processor is further configured to write an enable value to said register enabling said debug port while in said lowest mode of security.

8. The circuit according to claim 6, wherein said processor is further configured to write a disable value to said register disabling said debug port while in said intermediate mode of security.

9. A method of operating a circuit comprising the steps of:

(A) bootstrapping to a first memory while in a highest mode of security;

(B) disabling a debug port while in said highest mode of security;

(C) authenticating said debug port;

(D) disabling said debug port before transitioning to an intermediate mode of security in response to failing said authentication; and

(E) enabling said debug port while in a lowest mode of said security.

10. The method according to claim 9, further comprising the step of:

disabling said debug port while executing instructions from said first memory.

11. The method according to claim 9, further comprising the step of:

enabling said debug port in response to jumping to a second memory while in said lowest mode of security.

12. The method according to claim 11, further comprising the step of:

enabling said debug port in response to passing said authentication and jumping to said second memory.

13. The method according to claim 12, further comprising the step of:

disabling said debug port when jumping to a second memory in response to failing said authentication.

14. The method according to claim 11, further comprising the step of:

reading a multi-bit value from a third memory, wherein said multi-bit value is (i) represented by greater than two bits and (ii) distinguishes among said highest mode of security, said intermediate mode of security and said lowest mode of security.

15. The method according to claim 9, further comprising the step of:

masking an input signal generated external to said circuit and receivable by said debug port in response to disabling said debug port.

16. The method according to claim 9, further comprising the step of:

reading a security flag for said debug port from a one-time-programmable memory, wherein said security flag has at least three values.

17. The method according to claim 16, further comprising the step of:

enabling said debug port upon leaving said first memory in response to said security flag having a baseline value.

18. The method according to claim 17, further comprising the step of:

disabling said debug port upon leaving said first memory in response to said security flag having a locked value.

19. The method according to claim 18, further comprising the step of:

transmitting a challenge from a communication port to initiate authentication said debug port while executing from said first memory in response to said security flag having an authenticate value.

20. A circuit comprising:

means for bootstrapping to a first memory while in a highest mode of security;

means for disabling a debug port while in said highest mode of security;

means for authenticating said debug port;

means for disabling said debug port before transitioning to an intermediate mode of security in response to failing said authentication; and

means for enabling said debug port while in a lowest mode of said security.