Method for identifying an integrated circuit

• US 7,117,414 B2
• Filed: 04/22/2002
• Issued: 10/03/2006
• Est. Priority Date: 10/22/1999
• Status: Expired due to Fees

• Current Assignee: Infineon Technologies AG
• Original Assignee: Infineon Technologies AG
• Inventors: Hartmann, Ralf
• Primary Examiner(s): Lamarre, Guy
• Assistant Examiner(s): CHAUDRY, MUJTABA M
• Application Number:
  US10/127,615
• Publication Number:
  US 20020168815A1
• Time in Patent Office: 1,625 Days
• Field of Search: 714/718, 714/721, 714/724, 714/745, 714/42, 714/723, 365/158, 324/73.1, 324/433, 324/764, 340/636
• US Class Current: 714/733
• CPC Class Codes: G11C 16/20 Initialising; Data preset; Chip identification
• CPC Class Codes: G11C 2029/0407 on power on
• CPC Class Codes: G11C 2029/4402 Internal storage of test result, quality data, chip identification, repair information
• CPC Class Codes: G11C 29/08 Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
• CPC Class Codes: G11C 29/44 Indication or identification of errors, e.g. for repair
• CPC Class Codes: H01L 2223/5444 for electrical read out
• CPC Class Codes: H01L 23/544 Marks applied to semiconductor devices or parts, e.g. registration marks, alignment structures, wafer maps test patterns for characterising or monitoring manufacturing processes H01L22/00
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

An identifier is provided for an integrated circuit with a memory composed of a multiplicity of memory cells. The circuit has a manufacture-related memory cell defect pattern formed of defective memory cells. The method of identifying the integrated circuit utilizes the memory cell defect pattern to generate a circuit identification number for identifying the integrated circuit.

Claims

1. A method for identifying an integrated circuit having a memory including a multiplicity of memory cells and having a manufacture-related memory cell defect pattern including defective memory cells, the integrated circuit performing a self test when switched on, the method comprising:

acquiring addresses of defective memory cells from the self test of the integrated circuit;

generating a circuit identification number as a function of the addresses of defective memory cells for identifying the integrated circuit; and

comparing the circuit identification number with an original circuit identification number by an equipment program, the original circuit identification number being generated in a manufacturer test operation, the equipment program enabling a piece of equipment containing the integrated circuit if the circuit identification number generated in accordance with the self test is identical to the original circuit identification number.

2. The method according to claim 1, wherein

the circuit identification number is read out for linking to an equipment program to form an executable equipment program.

3. The method according to claim 2, wherein

the linked executable equipment program is stored in a program memory area in order to operate a piece of equipment.

4. The method according to claim 1, wherein the address of any defective memory cell is diverted in each case to an address of a backup memory cell in a redundant memory area of the memory.

5. The method according to claim 1, wherein, for each address of a defective memory cell, in each case an address of an associated backup memory cell is stored in an address conversion memory as an address table.

6. The method according to claim 1, wherein

the addresses of the defective memory cells are acquired once after manufacture of the integrated circuit in a manufacturer test and are permanently stored with the addresses of the associated backup memory cells in an address conversion memory for address diversion.

7. The method according to claim 1,

wherein the addresses of the defective memory cells are acquired in a self test whenever the integrated circuit is switched on and are stored with the addresses of the associated backup memory cells in the address conversion memory for address diversion.

8. The method according to claim 7, wherein

the circuit identification number is generated as a function of the addresses, acquired in the self test, of the defective memory cells and is compared with the linked original circuit identification number by the equipment program, the equipment program enabling the associated piece of equipment if the circuit identification number generated in accordance with the self test is identical to the original circuit identification number.

9. The method according to claim 1, wherein the circuit identification number is formed from one or more addresses of the defective memory cells.

10. The method according to claim 1, wherein the circuit identification number is generated by linking a plurality of addresses of the defective memory cells in a calculation operation for generating the circuit identification number.

11. A method for generating a circuit identification for identifying an integrated circuit having a memory including a multiplicity of memory cells and including a manufacture-related memory cell defect pattern including defective memory cells, the method comprising:

acquiring addresses of defective memory cells from a self test on the integrated circuit;

generating a circuit identification number as a function of the addresses of defective memory cells for identifying the integrated circuit; and

permanently storing the addresses of the defective memory cells with addresses of the associated backup memory cells in an address conversion memory of the integrated circuit for address diversion, the addresses of the defective memory cells identifying the integrated circuit.

12. The method according to claim 11, further comprising:

generating a circuit identification number for the integrated circuit as a function of the acquired addresses of the defective memory cells;

reading out the circuit identification number by a read-out program; and

linking the circuit identification number to an original equipment program to form an equipment program to be executed on the equipment.

13. The method according to claim 11, wherein, for each address of a defective memory cell, in each case the address of an associated backup memory cell is stored in an address conversion memory as an address table.

14. An integrated circuit identification method comprising the steps of:

providing an integrated circuit having a memory, including a multiplicity of memory cells and a manufacture-related memory cell defect pattern including defective memory cells;

performing a self test on the integrated circuit when switching on the integrated circuit for acquiring addresses of defective memory cells; and

generating a circuit identification number as a function of the addresses of defective memory cells for identifying the integrated circuit.