Methods for optimizing package and silicon co-design of integrated circuit

• US 7,117,467 B2
• Filed: 08/16/2004
• Issued: 10/03/2006
• Est. Priority Date: 08/16/2004
• Status: Active Grant

• Current Assignee: Bell Semiconductor, LLC (Hilco Inc. (d/b/a Hilco Global))
• Original Assignee: LSI Logic Corporation (Broadcom, Inc.)
• Inventors: Ali, Anwar, Mihelcic, Stan, Monthie, James G.
• Primary Examiner(s): Kik, Phallaka
• Application Number:
  US10/918,933
• Publication Number:
  US 20060036987A1
• Time in Patent Office: 778 Days
• Field of Search: 716/9, 716/10, 716/15, 438/108, 257/777, 257/778, 257/676, 257/678
• US Class Current: 716/122
• CPC Class Codes: G06F 30/39 Circuit design at the physical level physical level design for reconfigurable circuits G06F30/347

Abstract

The present invention is directed to methods for optimizing package and silicon co-design of an integrated circuit. A composite bump pattern for an integrated circuit is created based on a first library including at least one bump pattern template. PCB and Die constraints of the integrated circuit are then reviewed. A partial package design for the integrated circuit is generated based on a second library including at least one partial package template. A partial silicon design for said integrated circuit is started. A full package design for the integrated circuit is then completed. A full silicon design for the integrated circuit is completed.

Claims

1. A method for optimizing package and silicon co-design of an integrated circuit, comprising steps of:

creating, based on a first library including at least one bump pattern template, a composite bump pattern for an integrated circuit;

reviewing PCB and Die constraints of said integrated circuit;

generating, based on a second library including at least one partial package template, a partial package design for said integrated circuit;

starting a partial silicon design for said integrated circuit;

completing a full package design for said integrated circuit; and

completing a full silicon design for said integrated circuit.

2. The method of claim 1, wherein said creating step comprising:

selecting a plurality of bump pattern templates from said first library; and

assembling said plurality of bump pattern templates into said composite bump pattern.

3. The method of claim 1, wherein said creating step is performed through software automation.

4. The method of claim 1, wherein said at least one bump pattern template includes pre-designed die-based bump and flipchip interconnect patterns.

5. The method of claim 1, wherein said at least one bump pattern template is pre-characterized and defines at least one fixed package bump to IO circuit mapping.

6. The method of claim 1, wherein said at least one bump pattern template has fine or course granularity.

7. The method of claim 1, wherein said at least one bump pattern template includes at least one of a corner bump pattern template, a side bump pattern template, a SERDES bump pattern template, or a DDR bump pattern template.

8. The method of claim 1, wherein said at least one partial package template includes pre-defined substrate routing patterns from at least one die bump to at least one package ball.

9. The method of claim 1, wherein said first library and said second library are combined into a single library.

10. The method of claim 1, wherein said reviewing PCB and Die constraints of said integrated circuit comprising:

when said at least one bump pattern template fails to meet said PCB and Die constraints in a die region or a package pin-out of said integrated circuit, designing a new bump pattern template and adding said new bump pattern template to said first library.

11. The method of claim 1, wherein said generating step comprising:

selecting a plurality of partial package templates from said second library; and

assembling said plurality of partial package templates into said partial package design.

12. The method of claim 1, wherein said generating step is performed through software automation.

13. The method of claim 1, wherein said partial silicon design includes IO assignment.

14. The method of claim 1, further comprising using said full package design to reaffirm said partial package design.

15. The method of claim 1, further comprising completing a full electrical modeling of said integrated circuit.

16. A computer-readable medium having computer-executable instructions for performing a method for optimizing package and silicon co-design of an integrated circuit, said method comprising:

creating, based on a first library including at least one bump pattern template, a composite bump pattern for an integrated circuit;

reviewing PCB and Die constraints of said integrated circuit;

generating, based on a second library including at least one partial package template, a partial package design for said integrated circuit;

starting a partial silicon design for said integrated circuit;

completing a full package design for said integrated circuit; and

completing a full silicon design for said integrated circuit.

17. The computer-readable medium of claim 16, wherein said method further comprises completing a full electrical modeling of said integrated circuit.

18. A method for optimizing package and silicon co-design of an integrated circuit, comprising steps of:

creating, based on a first library including at least one bump pattern template, a composite bump pattern for an integrated circuit;

reviewing PCB and Die constraints of said integrated circuit;

generating, based on a second library including at least one partial package template, a full package design for said integrated circuit; and

completing a full silicon design for said integrated circuit.

19. The method of claim 18, wherein said creating step comprising:

selecting a plurality of bump pattern templates from said first library; and

assembling said plurality of bump pattern templates into said composite bump pattern.

20. The method of claim 18, wherein said creating step is performed through software automation.

21. The method of claim 18, wherein said at least one bump pattern template includes pre-designed die-based bump and flipchip interconnect patterns.

22. The method of claim 18, wherein said at least one bump pattern template is pre-characterized and defines at least one fixed package bump to IO circuit mapping.

23. The method of claim 18, wherein said at least one bump pattern template has fine or course granularity.

24. The method of claim 18, wherein said at least one bump pattern template includes at least one of a corner bump pattern template, a side bump pattern template, a SERDES bump pattern template, or a DDR bump pattern template.

25. The method of claim 18, wherein said at least one partial package template includes pre-defined substrate routing patterns from at least one die bump to at least one package ball.

26. The method of claim 18, wherein said first library and said second library are combined into a single library.

27. The method of claim 18, wherein said reviewing PCB and Die constraints of said integrated circuit comprising:

when said at least one bump pattern template fails to meet said PCB and Die constraints in a die region or a package pin-out of said integrated circuit, designing a new bump pattern template and adding said new bump pattern template to said first library.

28. The method of claim 18, wherein said generating step comprising:

selecting a plurality of partial package templates from said second library; and

assembling said plurality of partial package templates into said full package design.

29. The method of claim 18, wherein said generating step is performed through software automation.

30. The method of claim 18, further comprising completing a full electrical modeling for said integrated circuit.

31. A computer-readable medium having computer-executable instructions for performing a method for optimizing package and silicon co-design of an integrated circuit, said method comprising:

creating, based on a first library including at least one bump pattern template, a composite bump pattern for an integrated circuit;

reviewing PCB and Die constraints of said integrated circuit;

generating, based on a second library including at least one partial package template, a full package design for said integrated circuit; and

completing a full silicon design for said integrated circuit.

32. The computer-readable medium of claim 31, wherein said method further comprises completing a full electrical modeling for said integrated circuit.