Methods for optimizing package and silicon co-design of integrated circuit
First Claim
1. A method for optimizing package and silicon co-design of an integrated circuit, comprising steps of:
- creating, based on a first library including at least one bump pattern template, a composite bump pattern for an integrated circuit;
reviewing PCB and Die constraints of said integrated circuit;
generating, based on a second library including at least one partial package template, a partial package design for said integrated circuit;
starting a partial silicon design for said integrated circuit;
completing a full package design for said integrated circuit; and
completing a full silicon design for said integrated circuit.
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Accused Products
Abstract
The present invention is directed to methods for optimizing package and silicon co-design of an integrated circuit. A composite bump pattern for an integrated circuit is created based on a first library including at least one bump pattern template. PCB and Die constraints of the integrated circuit are then reviewed. A partial package design for the integrated circuit is generated based on a second library including at least one partial package template. A partial silicon design for said integrated circuit is started. A full package design for the integrated circuit is then completed. A full silicon design for the integrated circuit is completed.
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Citations
32 Claims
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1. A method for optimizing package and silicon co-design of an integrated circuit, comprising steps of:
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creating, based on a first library including at least one bump pattern template, a composite bump pattern for an integrated circuit; reviewing PCB and Die constraints of said integrated circuit; generating, based on a second library including at least one partial package template, a partial package design for said integrated circuit; starting a partial silicon design for said integrated circuit; completing a full package design for said integrated circuit; and completing a full silicon design for said integrated circuit. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15)
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16. A computer-readable medium having computer-executable instructions for performing a method for optimizing package and silicon co-design of an integrated circuit, said method comprising:
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creating, based on a first library including at least one bump pattern template, a composite bump pattern for an integrated circuit; reviewing PCB and Die constraints of said integrated circuit; generating, based on a second library including at least one partial package template, a partial package design for said integrated circuit; starting a partial silicon design for said integrated circuit; completing a full package design for said integrated circuit; and completing a full silicon design for said integrated circuit. - View Dependent Claims (17)
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18. A method for optimizing package and silicon co-design of an integrated circuit, comprising steps of:
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creating, based on a first library including at least one bump pattern template, a composite bump pattern for an integrated circuit; reviewing PCB and Die constraints of said integrated circuit; generating, based on a second library including at least one partial package template, a full package design for said integrated circuit; and completing a full silicon design for said integrated circuit. - View Dependent Claims (19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30)
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31. A computer-readable medium having computer-executable instructions for performing a method for optimizing package and silicon co-design of an integrated circuit, said method comprising:
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creating, based on a first library including at least one bump pattern template, a composite bump pattern for an integrated circuit; reviewing PCB and Die constraints of said integrated circuit; generating, based on a second library including at least one partial package template, a full package design for said integrated circuit; and completing a full silicon design for said integrated circuit. - View Dependent Claims (32)
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Specification