Method for high volume assembly of radio frequency identification tags

• US 7,117,581 B2
• Filed: 12/19/2002
• Issued: 10/10/2006
• Est. Priority Date: 08/02/2002
• Status: Active Grant

• Current Assignee: Symbol Technologies, LLC (Zebra Technologies Corporation)
• Original Assignee: Symbol Technologies, Inc. (Zebra Technologies Corporation)
• Inventors: Bandy, William R, Arneson, Michael R
• Primary Examiner(s): TRINH, MINH N
• Application Number:
  US10/322,467
• Publication Number:
  US 20040020036A1
• Time in Patent Office: 1,391 Days
• Field of Search: 296/00, 296/021, 298/25, 298/29, 29833-834, 235/492, 235/462, 235/13, 235/573.1, 340/572.7, 361/748, 361/736, 257/698
• US Class Current: 29/600
• CPC Class Codes: B29C 33/06 using radiation , e.g. electro-magnetic waves, induction heating
• CPC Class Codes: G06K 19/07718 the record carrier being manufactured in a continuous process, e.g. using endless rolls
• CPC Class Codes: G06K 19/07745 Mounting details of integrated circuit chips
• CPC Class Codes: G06K 19/07749 the record carrier being capable of non-contact communication, e.g. constructional details of the antenna of a non-contact smart card
• CPC Class Codes: G06K 19/0775 arrangements for connecting the integrated circuit to the antenna
• CPC Class Codes: G06K 19/07758 arrangements for adhering the record carrier to further objects or living beings, functioning as an identification tag
• CPC Class Codes: H01L 21/56 Encapsulations, e.g. encapsulation layers, coatings
• CPC Class Codes: H01L 21/6835 using temporarily an auxiliary support
• CPC Class Codes: H01L 2221/68354 used to support diced chips prior to mounting
• CPC Class Codes: H01L 2224/16 of an individual bump connector
• CPC Class Codes: H01L 2224/16225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/16227 the bump connector connecting to a bond pad of the item
• CPC Class Codes: H01L 2224/81191 wherein the bump connectors are disposed only on the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/83191 wherein the layer connectors are disposed only on the semiconductor or solid-state body
• CPC Class Codes: H01L 23/49855 for flat-cards, e.g. credit cards cards per se G06K19/00
• CPC Class Codes: H01L 24/96 the devices being encapsulated in a common layer, e.g. neo-wafer or pseudo-wafer, said common layer being separable into individual assemblies after connecting
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/01005 Boron [B]
• CPC Class Codes: H01L 2924/01006 Carbon [C]
• CPC Class Codes: H01L 2924/01013 Aluminum [Al]
• CPC Class Codes: H01L 2924/01027 : Cobalt [Co]
• CPC Class Codes: H01L 2924/01033 : Arsenic [As]
• CPC Class Codes: H01L 2924/01047 : Silver [Ag]
• CPC Class Codes: H01L 2924/01077 : Iridium [Ir]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/01082 : Lead [Pb]
• CPC Class Codes: H01L 2924/09701 : Low temperature co-fired ceramic [LTCC]
• CPC Class Codes: H01L 2924/12042 : LASER
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/19041 : being a capacitor
• CPC Class Codes: H01L 2924/19042 : being an inductor
• CPC Class Codes: H01L 2924/19043 : being a resistor
• CPC Class Codes: Y10T 156/10 : Methods of surface bonding and/or assembly therefor
• CPC Class Codes: Y10T 29/49016 : Antenna or wave energy "plumbing" making
• CPC Class Codes: Y10T 29/4902 : Electromagnet, transformer or inductor
• CPC Class Codes: Y10T 29/49117 : Conductor or circuit manufacturing
• CPC Class Codes: Y10T 29/49155 : Manufacturing circuit on or in base
• CPC Class Codes: Y10T 29/49826 : Assembling or joining
• CPC Class Codes: Y10T 29/49885 : with coating before or during assembling
• CPC Class Codes: Y10T 29/53039 : with control means energized in response to activator stimulated by condition sensor
• CPC Class Codes: Y10T 29/5313 : Means to assemble electrical device
• CPC Class Codes: Y10T 29/53178 : Chip component
• CPC Class Codes: Y10T 29/53191 : Means to apply vacuum directly to position or hold work part
• CPC Class Codes: Y10T 29/53261 : Means to align and advance work part

Abstract

A method for assembling a plurality of electronic devices is described. A plurality of dies separated die from a wafer are attached to a support surface. The plurality of dies is transferred from the support surface to a substrate structure that includes a plurality of tag substrates.

Claims

1. A method for assembling a plurality of radio frequency identification (RFID) tags, comprising:

(a) applying an underfill material on a surface of a substrate structure having an array of tag substrates;

(b) positioning a support surface closely adjacent to the surface of the substrate structure, such that each die of a plurality of dies attached to a first surface of the support surface is closely adjacent to a corresponding tag substrate of the array of tag substrates; and

(c) simultaneously transferring each die of the plurality of dies onto the closely adjacent corresponding tag substrate from the support surface.

2. The method of claim 1, wherein step (c) comprises:

applying a punching mechanism having a plurality of substantially co-planar punching portions to a second surface of the support surface, wherein a punching portion of the plurality of punching portions corresponds to each die of the plurality of dies.

3. The method of claim 1, further comprising:

curing the underfill material.

4. The method of claim 3, wherein the underfill material is an anisotropic electrically conductive material, wherein said curing step comprises:

flash curing the underfill material.

5. The method of claim 3, wherein the underfill material is a thermally curable epoxy, wherein said curing step comprises:

applying heat to cure the thermally curable epoxy.

6. The method of claim 3, wherein the underfill material is an acoustically curable epoxy, wherein said curing step comprises:

applying an acoustic source to cure the acoustically curable epoxy.

7. The method of claim 3, wherein the underfill material is an electron beam curable epoxy, wherein said curing step comprises:

applying an electron beam to cure the electron beam curable epoxy.

8. The method of claim 3, wherein the underfill material is an ultraviolet (UV) light wavelength curable epoxy, wherein said curing step comprises:

applying UV light to cure the UV light wavelength curable epoxy.

9. The method of claim 3, wherein the underfill material is an infrared (IR) light wavelength curable epoxy, wherein said curing step comprises:

applying IR light to cure the IR light wavelength curable epoxy.

10. The method of claim 3, wherein the underfill material is a pressure curable epoxy, wherein said curing step comprises:

applying a pressure between each die and corresponding tag substrate to cure the pressure curable epoxy.

11. The method of claim 3, wherein said curing step comprises:

causing the underfill material to contract to decrease a distance between each die and corresponding tag substrate to electrically couple each die to the corresponding tag substrate.

12. The method of claim 3, wherein the underfill material comprises electrically conductive microspheres to provide electrical connectivity, wherein said curing step comprises:

causing the underfill material to contract, which creates pressure between each die and corresponding tag substrate to cause the microspheres to at least deform to electrically couple each die to the corresponding tag substrate.

13. The method of claim 1, wherein the support surface is a chip carrier that has a plurality of cells accessible on a first surface of the chip carrier so that each die of the plurality of dies resides in a corresponding cell of the plurality of cells and is recessed in the corresponding cell with respect to the first surface, wherein step (c) comprises:

punching a second surface of the chip carrier proximate to a location opposite of each cell of the plurality of cells to move each die out of the corresponding cell.

14. The method of claim 13, wherein the plurality of tag substrate portions of the substrate structure are arranged a single column of tag substrate portions, wherein step (b) comprises:

aligning the substrate structure with the chip carrier.

15. The method of claim 14, wherein said aligning step comprises:

mechanically aligning the substrate structure with the chip carrier.

16. The method of claim 15, wherein said mechanically aligning step comprises:

aligning the chip carrier using a first wheel having spaced pegs that interlock with spaced holes in the chip carrier;

aligning the substrate structure using a second wheel having spaced pegs that interlock with spaced holes in the substrate structure, wherein the first wheel and second wheel are synchronized.

17. The method of claim 14, wherein said aligning step comprises:

optically aligning the substrate structure with the chip carrier.

18. The method of claim 13, wherein each die has at least one contact pad located on a first surface, further comprising:

prior to step (b), inserting each die in the corresponding cell such that the first surface with the at least one contact pad faces into the cell.

19. The method of claim 13, further comprising:

(d) prior to step (b), forming the plurality of cells in the chip carrier.

20. The method of claim 19, wherein step (d) comprises:

forming a plurality of serially aligned openings through the chip carrier that are open on the first surface and a second surface of the chip carrier; and

applying an adhesive structure to the second surface of the chip carrier to cover the plurality of serially aligned openings on the second surface of the chip carrier.

21. The method of claim 1, further comprising:

(d) prior to step (b), separating the plurality of dies from a wafer attached to the support surface so that the plurality of dies are separated and attached to the support surface.

22. The method of claim 21, further comprising:

(e) prior to step (d), attaching the wafer to the support surface.

23. The method of claim 1, wherein the plurality of dies is all of the dies attached to the first surface of the support surface, wherein step (c) comprises:

simultaneously transferring all of the dies attached to the first surface of the support surface.

24. The method of claim 1, wherein the plurality of dies is a portion of the dies attached to the first surface of the support surface, wherein step (c) comprises:

simultaneously transferring a portion of the dies attached to the first surface of the support surface.