Method of isolating the current sense on power devices while maintaining a continuous stripe cell

• US 7,118,951 B2
• Filed: 05/17/2005
• Issued: 10/10/2006
• Est. Priority Date: 01/22/2002
• Status: Expired due to Term

• Current Assignee: Semiconductor Components Industries LLC (ON Semiconductor Corporation)
• Original Assignee: Fairchild Semiconductor Corporation (ON Semiconductor Corporation)
• Inventors: Yedinak, Joseph A., Reichl, Dwayne S., Lange, Douglas J.
• Primary Examiner(s): Blum, David S.
• Application Number:
  US11/130,794
• Publication Number:
  US 20050272209A1
• Time in Patent Office: 511 Days
• Field of Search: 438/197, 438/281, 438/333, 438/587
• US Class Current: 438/197
• CPC Class Codes: H01L 29/0696 of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
• CPC Class Codes: H01L 29/7395 Vertical transistors, e.g. vertical IGBT
• CPC Class Codes: H01L 29/7815 with voltage or current sensing structure, e.g. emulator section, overcurrent sensing cell

Abstract

An integrated circuit die includes an active area having source dopants and contacts. An active area metal layer overlies the active area. A sense area is disposed on the die. A sense area metal layer overlies the sense area. A plurality of polysilicon gate stripes, polysilicon openings, and body stripes are disposed on the die, and extend in a continuous and uninterrupted manner from the active area into the sense area. A first region from which source dopants and contacts have been excluded surrounds a periphery of the sense area. An etched region is disposed over the first region, thereby separating and electrically isolating the sense area metal layer from the active area metal layer.

Claims

1. On an integrated circuit die, a method of isolating a current sense area from a main device active area while maintaining a continuous stripe cell, the sense area having an overlying sense metal layer, the main device active area having an overlying active metal layer, said method comprising:

fabricating on the die a plurality of polysilicon gate stripes, polysilicon openings, and body stripes that extend in a continuous and uninterrupted manner from the active area into the sense area;

excluding source dopants and contact from a first region that surrounds the periphery of the sense area; and

breaking the active area metal layer over the first region to thereby electrically isolate the sense area from the active area.

2. The method of claim 1, wherein said first region extends at least partially into each of said sense area and said main device area.

3. The method of claim 1, comprising the further step of excluding source dopants from a source exclude region of the sense area.

4. The method of claim 3 comprising the further step of doping a source region of the sense area with source dopants.

5. The method of claim 4, wherein said source region surrounds said source exclude region.

6. The method of claim 1, wherein said breaking step comprises etching the active area metal layer over the first region.

7. The method of claim 1, comprising the further step of electrically connecting said sense area to a control circuit integral and monolithic with the die.

8. The method of claim 1, wherein the integrated circuit is one of an integrated gate bipolar transistor and a metal oxide field effect transistor.

9. The method of claim 8, wherein the transistor is a trench stripe device.