Methods of fabricating silicon carbide devices with hybrid well regions

• US 7,118,970 B2
• Filed: 06/22/2004
• Issued: 10/10/2006
• Est. Priority Date: 06/22/2004
• Status: Active Grant

• Current Assignee: CREE Incorporated (Wolfspeed, Inc.)
• Original Assignee: CREE Incorporated (Wolfspeed, Inc.)
• Inventors: Das, Mrinal Kanti, Ryu, Sei-Hyung
• Primary Examiner(s): Smith, Matthew
• Assistant Examiner(s): STARK, JARRETT J
• Application Number:
  US10/873,394
• Publication Number:
  US 20050280004A1
• Time in Patent Office: 840 Days
• Field of Search: 438/268, 438/105, 438/519, 438/418, 438/419, 438/518, 438/931, 257/331, 257/328, 257/77
• US Class Current: 438/268
• CPC Class Codes: H01L 29/0615 by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE] LDD or drain offset regions H01L29/7833
• CPC Class Codes: H01L 29/0661 specially adapted for altering the breakdown voltage by removing semiconductor material at, or in the neighbourhood of, a reverse biased junction, e.g. by bevelling, moat etching, depletion etching
• CPC Class Codes: H01L 29/0878 Impurity concentration or distribution
• CPC Class Codes: H01L 29/1095 Body region, i.e. base region, of DMOS transistors or IGBTs cell layout H01L29/0696
• CPC Class Codes: H01L 29/1608 Silicon carbide
• CPC Class Codes: H01L 29/66068 the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
• CPC Class Codes: H01L 29/7395 Vertical transistors, e.g. vertical IGBT
• CPC Class Codes: H01L 29/7802 Vertical DMOS transistors, i.e. VDMOS transistors
• CPC Class Codes: Y10S 438/931 Silicon carbide semiconductor

Abstract

MOS channel devices and methods of fabricating such devices having a hybrid channel are provided. Exemplary devices include vertical power MOSFETs that include a hybrid well region of silicon carbide and methods of fabricating such devices are provided. The hybrid well region may include an implanted p-type silicon carbide well portion in a p-type silicon carbide epitaxial layer, an implanted p-type silicon carbide contact portion that contacts the implanted p-type silicon carbide well portion and extends to a surface of the p-type epitaxial layer and/or an epitaxial p-type silicon carbide portion, at least a portion of the epitaxial p-type silicon carbide well portion corresponding to a p-type channel region of the MOSFET.

Claims

1. A method of fabricating a silicon carbide MOSFET, comprising:

forming a hybrid p-type silicon carbide well region on a silicon carbide substrate having a drift region, the hybrid p-type silicon carbide well region comprising;

an implanted p-type silicon carbide well portion in a p-type silicon carbide epitaxial layer;

an implanted p-type silicon carbide contact portion that contacts the implanted p-type silicon carbide well portion and extends to a surface of the p-type epitaxial layer; and

an epitaxial p-type silicon carbide portion, at least a portion of the epitaxial p-type silicon carbide portion corresponding to a p-type channel region of the MOSFET;

forming a first n-type silicon carbide region at least in part within the hybrid p-type silicon carbide well region;

forming a second n-type silicon carbide region adjacent the p-type channel region and extending to the drift region to provide an n-type channel region;

forming a gate dielectric on the second n-type silicon carbide and at least a portion of the first n-type silicon carbide region;

forming a gate contact on the gate dielectric;

forming a first contact so as to contact a portion of the contact portion of the hybrid p-type silicon carbide well region the first n-type silicon carbide region; and

forming a second contact on the substrate.

2. The method of claim 1, wherein the drift region is an n-type silicon carbide drift region and wherein forming a hybrid p-type silicon carbide well region comprises:

forming a p-type silicon carbide epitaxial layer on the n-type silicon carbide drift region;

forming a buried p-type silicon carbide region in the p-type silicon carbide epitaxial layer, the buried p-type region having a higher carrier concentration than a carrier concentration of the p-type epitaxial layer; and

forming a second p-type silicon carbide region in the p-type silicon carbide epitaxial region that extends from the buried p-type region to a surface of the p-type silicon carbide epitaxial layer.

3. The method of claim 2, wherein forming a buried p-type silicon carbide region comprises:

forming a first ion implantation mask on the p-type silicon carbide epitaxial layer, the first ion implantation mask having an opening corresponding to a location of the buried p-type silicon carbide region;

implanting p-type dopants in the p-type epitaxial layer utilizing the first ion implantation mask; and

wherein forming a first n-type silicon carbide region comprises implanting n-type dopants in the p-type epitaxial layer utilizing the first ion implantation mask.

4. The method of claim 3, wherein forming a second p-type silicon carbide region comprises:

forming a second ion implantation mask on the p-type silicon carbide epitaxial layer, the second ion implantation mask having an opening corresponding to a location of the second p-type silicon carbide region; and

implanting p-type dopants in the p-type epitaxial layer utilizing the second ion implantation mask.

5. The method of claim 4, wherein forming a second n-type silicon carbide region comprises:

forming a third ion implantation mask on the p-type silicon carbide epitaxial layer, the third ion implantation mask having an opening corresponding to a location of the second n-type silicon carbide region; and

implanting n-type dopants in the p-type epitaxial layer utilizing the third ion implantation mask.

6. The method of claim 5, further comprising activating the implanted n-type and p-type dopants by exposing the p-type epitaxial layer to a temperature of from about 1200°

C. to about 1800°

C.

7. The method of claim 6, wherein activating the implanted n-type and p-type dopants is preceded by capping exposed portions of the p-type epitaxial layer with a passivating material.

8. The method of claim 7, wherein forming a gate dielectric comprises patterning the passivating material so as to provide the gate dielectric.

9. The method of claim 1, further comprising forming a voltage absorbing region around the silicon carbide device MOSFET.

10. The method of claim 1, wherein the drift region comprises an n-type silicon carbide epitaxial layer on the silicon carbide substrate and wherein the p-type epitaxial layer is formed on the n-type silicon carbide epitaxial layer.

11. A method of fabricating a silicon carbide power device, comprising:

forming a first p-type silicon carbide epitaxial layer on an n-type silicon carbide drift region on an n-type silicon carbide substrate;

forming at least one first region of n-type silicon carbide through the first p-type silicon carbide epitaxial layer and extending to the n-type silicon carbide drift region so as to provide at least one channel region in the first p-type silicon carbide epitaxial layer;

forming at least one second region of n-type silicon carbide in the first p-type silicon carbide epitaxial layer which is adjacent and spaced apart from the first region of n-type silicon carbide;

implanting p-type dopants in the p-type silicon carbide epitaxial layer to form at least one buried region of p-type silicon carbide in the first p-type silicon carbide epitaxial layer, the at least one buried region having a higher carrier concentration than the p-type silicon carbide epitaxial layer and being positioned between the at least one second region of n-type silicon carbide and the drift region and being substantially aligned with a side of the at least one second region of n-type silicon carbide adjacent the at least one first region of n-type silicon carbide;

implanting p-type dopants in the p-type silicon carbide epitaxial layer to form at least one contact region of p-type silicon carbide that extends through the at least one second region of n-type silicon carbide to the at least one buried region of p-type silicon carbide; and

forming a gate dielectric on the first region of n-type silicon carbide and at least a portion of the second region of n-type silicon carbide.

12. The method of claim 11, further comprising:

forming a gate contact on the gate dielectric;

forming a first contact so as to contact a portion of the contact region of p-type silicon carbide and the second region of n-type silicon carbide; and

forming a second contact on the substrate.

13. The method of claim 11, wherein forming at least one second region of n-type silicon carbide and implanting p-type dopants in the p-type silicon carbide epitaxial layer to form at least one buried region comprises:

patterning a first mask layer on the p-type epitaxial layer, the first mask layer having an opening corresponding to the at least one second region of n-type silicon carbide and the at least one buried region;

implanting p-type dopants utilizing the patterned first mask layer to provide the at least one buried region; and

implanting n-type dopants utilizing the patterned first mask layer to provide the at least one second region of n-type silicon carbide.

14. The method of claim 13, wherein implanting n-type dopants and implanting p-type dopants in the p-type silicon carbide epitaxial layer are followed by activating the implanted n-type dopants and p-type dopants.

15. The method of claim 14, wherein activating the implanted n-type dopants and p-type dopants comprises exposing the implanted first p-type epitaxial layer to a temperature of from about 1200°

C. to about 1800°

C.

16. The method of claim 15, wherein exposing the implanted first p-type epitaxial layer is preceded by capping exposed portions of the first p-type epitaxial layer with a passivating material.

17. The method of claim 16, wherein forming a gate dielectric comprises patterning the passivating material so as to provide the gate dielectric.

18. The method of claim 13, wherein implanting p-type dopants in the p-type silicon carbide epitaxial layer to form at least one contact region of p-type silicon carbide comprises:

forming a second mask layer on the p-type silicon carbide epitaxial layer, the second mask layer having an opening corresponding to a location of the at least one contact region; and

implanting p-type dopants in the p-type epitaxial layer utilizing the second mask layer.

19. The method of claim 18, wherein forming at least one second region of n-type silicon carbide region comprises:

forming a third mask layer on the p-type silicon carbide epitaxial layer, the third mask layer having an opening corresponding to a location of the at least one second region of n-type silicon carbide; and

implanting n-type dopants in the p-type epitaxial layer utilizing the third mask layer.

20. A method of claim 11, further comprising forming a voltage absorbing region around the silicon carbide device.

21. The method of claim 11, further comprising forming an n-type silicon carbide epitaxial layer on the silicon carbide substrate, the n-type silicon carbide epitaxial layer providing the n-type drift region.

22. The method of claim 11, wherein the at least one buried region extends to the drift region.

23. A method of fabricating a silicon carbide Metal-Oxide Semiconductor (MOS) gated device, comprising:

forming a hybrid silicon carbide well region of a first conductivity type, comprising;

forming a first silicon carbide epitaxial layer of a first conductivity type;

implanting a ions in the silicon carbide epitaxial layer to provide an implanted well portion of the first conductivity type in the silicon carbide epitaxial layer; and

implanting ions in the silicon carbide epitaxial layer to provide an implanted contact portion that contacts the implanted well portion and extends to a surface of the epitaxial layer;

forming a first silicon carbide region of a second conductivity type at least in part within the hybrid silicon carbide well region;

forming a second silicon carbide region of the second conductivity type adjacent the well region and spaced apart from the first silicon carbide region;

forming a gate dielectric on the second silicon carbide region and at least a portion of the first silicon carbide region;

forming a gate contact on the gate dielectric; and

where an unimplanted portion of the epitaxial layer corresponds to a channel region of the device.

24. The method of claim 23, wherein the first conductivity type is p-type and the second conductivity type is n-type.

25. The method of claim 23, wherein the first conductivity type is n-type and the second conductivity type is p-type.

26. The method of claim 23, wherein forming an epitaxial layer comprises forming an epitaxial layer on a drift region of the second conductivity type, the first region of silicon carbide extends to the drift region and wherein the device comprises a field effect transistor.

27. The method of claim 26, wherein the drift region comprises an epitaxial layer of silicon carbide.

28. The method of claim 26, wherein the drift region comprises a silicon carbide substrate.

29. The method of claim 23, wherein forming an epitaxial layer comprises forming an epitaxial layer on a layer of first conductivity type silicon carbide, the first region of silicon carbide extends to the layer of first conductivity type silicon carbide and wherein the device comprises an insulated gate bipolar transistor.

30. The method of claim 29, wherein the layer of first conductivity silicon carbide comprises an epitaxial layer of silicon carbide.

31. The method of claim 29, wherein the layer of first conductivity type silicon carbide comprises a silicon carbide substrate.