Wafer thinning using magnetic mirror plasma

• US 7,118,992 B2
• Filed: 08/09/2004
• Issued: 10/10/2006
• Est. Priority Date: 10/26/2001
• Status: Expired due to Fees

• Current Assignee: iFire Technology Inc.
• Original Assignee: iFire Technology Inc.
• Inventors: Turner, Terry R., Spain, James D., Banks, Richard M.
• Primary Examiner(s): Smoot, Stephen W.
• Application Number:
  US10/914,248
• Publication Number:
  US 20050032333A1
• Time in Patent Office: 792 Days
• Field of Search: 438/113, 438/458, 438/459, 438/462, 438/464, 438/691, 438/977, 438/728, 438/730, 438/732, 204/298.37, 422/186.01
• US Class Current: 438/459
• CPC Class Codes: H01L 21/304 Mechanical treatment, e.g. grinding, polishing, cutting H01L21/30625 takes precedence
• CPC Class Codes: H01L 21/3065 Plasma etching; Reactive-ion etching
• CPC Class Codes: H01L 21/76898 formed through a semiconductor substrate
• CPC Class Codes: H01L 21/78 with subsequent division of the substrate into plural individual devices cutting to change the surface-physical characteristics or shape of semiconductor bodies H01L21/304
• CPC Class Codes: H01L 23/481 Internal lead connections, e.g. via connections, feedthrough structures
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00012 Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: Y10S 438/977 Thinning or removal of substrate

Abstract

A method for manufacturing integrated circuits uses an atmospheric magnetic mirror plasma etching apparatus to thin a semiconductor wafer. In addition the process may, while thinning, both segregate and expose through-die vias for an integrated circuit chip. To segregate, the wafer may be partially diced. Then, the wafer may be tape laminated. Next, the backside of the wafer may be etched. As the backside material is removed, the partial dicing and through-die vias may be exposed. As such, the method reduced handling steps and increases yield. Furthermore, the method may be used in association with wafer level processing and flip chip with bump manufacturing.

Claims

1. A method for segregating an integrated circuitry chip from a wafer, the method comprising:

circumscribing the integrated circuitry chip with at least one recess, said at least one recess having a particular depth extending into the wafer from a front side of the wafer;

etching bulk wafer material from a back side of the wafer to achieve a particular thickness of the wafer, said thickness of the wafer being at most equal to said particular depth, said etching step comprising use of a magnetic mirror plasma; and

magnetically steering ions within said magnetic mirror plasma for varying the angular momentum of said ions along magnetic mirror field lines, thereby varying activation energy of said ions for controlling etching characteristics of said ions.

2. The method of claim 1, wherein said step of etching bulk wafer material further comprises the step of using an orthogonally rotating electric field for controlling the etch characteristics of said magnetic mirror plasma.

3. The method of claim 1 wherein said step of etching bulk wafer material further comprises the step of sweeping a E x B field drift vector in a radial direction perpendicular to the magnetic mirror field lines.

4. The method of claim 1 wherein said step of etching bulk wafer material further comprises the step of achieving a particular thickness of the wafer at most equal to a depth of at least one integrated circuitry feature.

5. The method of claim 1, the method further comprising the step of forming a recess extending from the front side of the wafer, the recess having a depth at least equal to said particular depth.

6. The method of claim 1, the method further comprising the step of etching bulk wafer material from said wafer with out moving said wafer during said etching process.

7. A system for segregating an integrated circuitry chip from a wafer, the system comprising:

a plasma etching mechanism for circumscribing the integrated circuitry chip with at least one recess on a front side of the wafer, said at least one recess having a particular depth;

said plasma etching mechanism comprising an etching means for removing bulk wafer material from a back side of the wafer to achieve a particular thickness of the wafer, said particular thickness of the wafer being at most equal to said particular depth, wherein said etching means comprises a magnetic mirror plasma; and

magnetic ion steering circuitry associated with said plasma etching mechanism for magnetically steering ions within said magnetic mirror plasma for varying the angular momentum of said ions along magnetic mirror field lines, thereby varying activation energy of said ions for controlling etching characteristics of said ions.

8. The system of claim 7, wherein magnetic ion steering circuitry further comprises circuitry for providing and controlling an orthogonally rotating electric field for varying the etch characteristics of said magnetic mirror plasma.

9. The system of claim 7, wherein said magnetic ion steering circuitry further comprises circuitry for sweeping a E x B field drift vector in a radial direction perpendicular to the magnetic mirror field lines.

10. The system of claim 7, wherein said plasma etching mechanism further comprises circuitry for achieving said particular thickness of the wafer at most equal to said particular depth of at least one integrated circuitry feature.

11. The system of claim 7, further comprising a laminating mechanism for laminating said front side of the wafer.

12. The system of claim 7, the etching means for removing a residue material from said back side of the wafer.

13. The system of claim 7, the system further comprising a recess means for forming a recess extending from said front side of the wafer, said recess having a depth at least equal to said particular depth.

14. A method for segregating an integrated circuitry chip from a wafer and exposing at least one integrated circuitry feature, the at least one integrated circuitry feature having a depth extending from a front side of the wafer, the method comprising:

circumscribing the integrated circuitry chip with at least one recess on the front side of the wafer, said at least one recess having a particular depth;

etching bulk wafer material from a back side of the wafer to achieve a particular thickness of the wafer, said thickness of the wafer being at most equal to said depth of the at least one integrated circuitry feature and at most equal to said particular depth, said etching step using a magnetic mirror plasma; and

magnetically steering ions within said magnetic mirror plasma for varying the angular momentum of said ions along magnetic mirror field lines, thereby varying activation energy of said ions for controlling etching characteristics of said ions.

15. The method of claim 14, further comprising the step of symmetrically driving the formation of said magnetic mirror plasma.

16. The method of claim 14, further comprising the step of asymmetrically driving the formation of said magnetic mirror plasma.

17. The method of claim 14, further comprising the step of controlling said magnetic mirror plasma using a magnetic mirror field and an orthogonally rotating electric field.

18. The method of claim 14, further comprising the step of varying the axial magnetic field density of said magnetic mirror plasma using an orthogonally rotating electric field.

19. The method of claim 18, further comprising the steps of creating said ions remotely from the plasma chamber.

20. The method of claim 14, wherein said step of etching bulk wafer material further comprises the step of sweeping a E x B field drift vector in a radial direction perpendicular to the magnetic mirror field lines.