Process integration of SOI FETs with active layer spacer

• US 7,119,023 B2
• Filed: 10/16/2003
• Issued: 10/10/2006
• Est. Priority Date: 10/16/2003
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Liaw, Jhon Jhy
• Primary Examiner(s): CHEN, KIN CHAN
• Application Number:
  US10/687,424
• Publication Number:
  US 20050085081A1
• Time in Patent Office: 1,090 Days
• Field of Search: 438/700, 438/702, 438/703, 438/706, 438/710, 438/714, 438/719, 438/724
• US Class Current: 438/719
• CPC Class Codes: H01L 21/02046 Dry cleaning only H01L21/02085 takes precedence
• CPC Class Codes: H01L 21/02052 Wet cleaning only H01L21/02085 takes precedence
• CPC Class Codes: H01L 21/84 the substrate being other than a semiconductor body, e.g. being an insulating body
• CPC Class Codes: H01L 27/1203 the substrate comprising an insulating body on a semiconductor body, e.g. SOI three-dimensional layout H01L27/0688
• CPC Class Codes: H01L 29/458 for thin film silicon, e.g. source or drain electrode
• CPC Class Codes: H01L 29/66772 Monocristalline silicon transistors on insulating substrates, e.g. quartz substrates H01L29/66666 takes precedence; thin film FinFETs H01L29/66795
• CPC Class Codes: H01L 29/7842 means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate variation of the composition of the channel H01L29/1054
• CPC Class Codes: H01L 29/78687 with a multilayer structure or superlattice structure

Abstract

A method of manufacturing a microelectronics device including providing a substrate having an active layer, a dielectric layer and a structural layer, wherein the active layer is formed over the dielectric layer and the dielectric layer is formed over the structural layer. The method further includes forming an opening through the active layer thereby exposing a surface of the dielectric layer and defining active layer sidewalls. A spacer is formed covering a first portion of the exposed dielectric layer surface and substantially spanning one of the active layer sidewalls. At least a second portion of the exposed dielectric layer surface is then cleaned.

Claims

1. A method of manufacturing a microelectronic device, comprising:

providing a substrate having an active layer, a dielectic layer and a structural layer, wherein the active layer is formed over the dielectric layer and the dielectric layer is formed over the structural layer;

forming an opening through the active layer thereby exposing a surface of the dielectric layer and defining active layer sidewalls;

cleaning the exposed surface of the dielectric layer, wherein the cleaning includes plasma cleaning employing an etch chemistry containing at least one of fluorine and a fluorine-containing gas, and then forming a spacer covering a portion of the cleaned, exposed dielectric layer surface and substantially spanning one of the active layer sidewalls; and

forming a gate electrode over the active layer.

2. The method of claim 1 further comprising forming an etch stop layer over the active layer, wherein the opening is formed through the active layer and the etch stop layer thereby defining etch stop layer sidewalls substantially aligned with the active layer sidewalls, wherein the spacer substantially spans one of the active layer sidewalls, and one of the etch stop layer sidewalls, and wherein the cleaning is performed after forming the opening though the active layer and the etch stop layer and before forming the spacer.

3. The method of claim 1 wherein the cleaning further includes chemical etching with an etchant chemistry comprising hydrofluoric acid.

4. The method of claim 1 wherein the cleaning further includes vapor etching.

5. The method of claim 1 further comprising forming a silicide layer over the active layer.

6. The method of claim 1 wherein the spacer comprises silicon dioxide.

7. The method of claim 1 wherein the active layer comprises strained silicon.

8. The method of claim 1 wherein the active layer has a thickness ranging between about 100 Angstroms and about 1000 Angstroms.

9. The method of claim 1 wherein the active layer comprises a silicon layer, a silicon germanium layer, and a strained silicon layer, wherein the silicon germanium layer is located over the silicon Layer, and wherein the strained silicon layer is located over the silicon germanium layer.

10. The method of claim 1 wherein the active layer comprises a plurality of layers including a strained silicon layer.

11. The method of claim 1 wherein the active layer comprises a plurality of layers.

12. A method of manufacturing a microelectronic device, comprising:

providing a substrate having;

a structural layer;

a dielectric layer located on the structural layer; and

an active layer located on the dielectric layer;

forming an opening through the active layer thereby exposing a surface of the dielectric layer and defining active layer sidewalls;

cleaning the exposed surface of the dielectric layer, wherein the cleaning includes plasma cleaning employing an etch chemistry containing at least one of fluorine and a fluorine-containing gas, and then forming a spacer covering at least a portion of the cleaned, exposed dielectric layer surface and spanning at least a portion of the active layer sidewalls; and

forming a gate electrode on the active layer.

13. The method of claim 12 further comprising forming an etch stop layer over the active layer, wherein the opening is formed through the active layer and the etch stop layer thereby defining etch stop layer sidewalls substantially aligned with the active layer sidewalls, wherein the spacer substantially spans one of the active layer sidewalls and one of the etch stop layer sidewalls, and wherein the cleaning is performed after forming the opening through the active layer and the etch stop layer and before forming the spacer.

14. The method of claim 12 wherein the cleaning further includes chemical etching with an etchant chemistry comprising hydrofluoric acid.

15. The method of claim 12 wherein the cleaning further includes vapor etching.

16. The method of claim 12 further comprising forming a silicide layer over the active layer.

17. The method of claim 12 wherein the spacer comprises silicon dioxide.

18. The method of claim 12 wherein the active layer comprises strained silicon.

19. The method of claim 12 wherein the active layer has a thickness ranging between about 100 Angstroms and about 1000 Angstroms.

20. The method of claim 12 wherein the active layer comprises a silicon layer, a silicon germanium layer, and a strained silicon layer, wherein the silicon germanium layer is located over the silicon layer, and wherein the strained silicon layer is located over the silicon germanium layer.

21. The method of claim 12 wherein the active layer comprises a plurality of layers including a strained silicon layer.

22. The method of claim 12 wherein the active layer comprises a plurality of layers.