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Process integration of SOI FETs with active layer spacer

  • US 7,119,023 B2
  • Filed: 10/16/2003
  • Issued: 10/10/2006
  • Est. Priority Date: 10/16/2003
  • Status: Active Grant
First Claim
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1. A method of manufacturing a microelectronic device, comprising:

  • providing a substrate having an active layer, a dielectic layer and a structural layer, wherein the active layer is formed over the dielectric layer and the dielectric layer is formed over the structural layer;

    forming an opening through the active layer thereby exposing a surface of the dielectric layer and defining active layer sidewalls;

    cleaning the exposed surface of the dielectric layer, wherein the cleaning includes plasma cleaning employing an etch chemistry containing at least one of fluorine and a fluorine-containing gas, and then forming a spacer covering a portion of the cleaned, exposed dielectric layer surface and substantially spanning one of the active layer sidewalls; and

    forming a gate electrode over the active layer.

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