Implantation method to improve ESD robustness of thick gate-oxide grounded-gate NMOSFET's in deep-submicron CMOS technologies

• US 7,119,405 B2
• Filed: 02/11/2005
• Issued: 10/10/2006
• Est. Priority Date: 02/11/2005
• Status: Expired due to Fees

• Current Assignee: Avago Technologies General IP PTE Limited (Broadcom, Inc.)
• Original Assignee: LSI Logic Corporation (Broadcom, Inc.)
• Inventors: Chen, Jau-Wen, Huh, Yoon, Li, Erhong
• Primary Examiner(s): Parker, Kenneth
• Assistant Examiner(s): Fenty, Jesse A.
• Application Number:
  US11/056,641
• Publication Number:
  US 20060180863A1
• Time in Patent Office: 606 Days
• Field of Search: 257/392, 257/355, 257/546, 257/391, 257/336, 257/344, 257/408, 257/E21.443
• US Class Current: 257/391
• CPC Class Codes: H01L 21/823814 with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures
• CPC Class Codes: H01L 21/823857 with a particular manufacturing method of the gate insulating layers, e.g. different gate insulating layer thicknesses, particular gate insulator materials or particular gate insulator implants
• CPC Class Codes: H01L 27/027 specially adapted to provide an electrical current path other than the field effect induced current path
• CPC Class Codes: H01L 29/7833 with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's for thin film transistors H01L29/78618

Abstract

An implantation method to improve ESD robustness of thick-oxide grounded-gate NMOSFET'"'"'s in deep-submicron CMOS technologies. Based on standard process flow in DGO, a thick gate-oxide ESD device is improved. Instead of using the standard I/O device, the ESD device uses the thin-oxide N-LDD implantation, and thus its ESD robustness is enhanced. This is performed by updating the logic Boolean operations of thick gate-oxide and thin gate-oxide N-LDD before fabricating the masks. In TGO, the intermediate-oxide ESD uses thin-oxide N-LDD implantation, and the thick-oxide ESD uses intermediate-oxide N-LDD implantation.

Claims

1. An ESD protection circuit of a thick gate-oxide grounded-gate NMOSFET, said ESD protection circuit comprising:

a substrate;

a thick-oxide on the substrate;

a first spacer on the substrate proximate the thick-oxide; and

thin-oxide N-LDD implantation under the first spacer in the substrate;

wherein the NMOSFET comprises an I/O which comprises a thick-oxide, a second spacer proximate the thick-oxide of the I/O, and thick-oxide N-LDD implantation disposed under the second spacer, wherein the thin-oxide N-LDD implantation has a higher doping concentration than does the thick-oxide N-LDD implantation which is disposed under the second spacer;

wherein the NMOSFET comprises a core which comprises a thin-oxide, a third spacer proximate the thin-oxide of the core, and thin-oxide N-LDD implantation disposed under the third spacer, wherein the thin-oxide N-LDD implantation has substantially the same doping concentration than does the thin-oxide N-LDD implantation which is disposed under the third spacer.

2. An ESD protection circuit as recited in claim 1, wherein the thin-oxide N-LDD implantation in the substrate is disposed generally between contacts of the thick gate-oxide grounded-gate NMOSFET and the thick gate-oxide.

3. An ESD protection circuit as recited in claim 1, wherein the ESD protection circuit is configured to provide ESD protection without utilizing a floating gate transistor.