Apparatus and method for forming heat sinks on silicon on insulator wafers

• US 7,119,431 B1
• Filed: 09/18/2003
• Issued: 10/10/2006
• Est. Priority Date: 09/18/2003
• Status: Active Grant

• Current Assignee: National Semiconductor Corporation (Texas Instruments, Inc.)
• Original Assignee: National Semiconductor Corporation (Texas Instruments, Inc.)
• Inventors: Vashchenko, Vladislav, Johnson, Peter, Hopper, Peter J., Mirgorodski, Iouri
• Primary Examiner(s): Smith, Zandra V.
• Assistant Examiner(s): BRYANT, KIESHA ROSE
• Application Number:
  US10/665,897
• Time in Patent Office: 1,118 Days
• Field of Search: 257/774, 257/347, 257/706
• US Class Current: 257/706
• CPC Class Codes: H01L 23/3677 Wire-like or pin-like cooling fins or heat sinks
• CPC Class Codes: H01L 23/481 Internal lead connections, e.g. via connections, feedthrough structures
• CPC Class Codes: H01L 29/78606 with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device H01L29/78642, H01L29/78645 take precedence
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

An apparatus and method for a heat sink to dissipate the heat sourced by the encapsulated transistors in a SOI wafer. The apparatus includes a transistor formed in the active silicon layer of the wafer. The active surface is formed over an oxide layer and a bulk silicon layer. A heat sink is formed in the bulk silicon layer and configured to sink heat through the bulk silicon layer, to the back surface of the wafer. After the transistor is fabricated, the heat sink is formed by masking, patterning and etching the back surface of the wafer to form plugs in the bulk silicon layer. The plug extends through the thickness of the bulk layer to the oxide layer. Thereafter, the plug is filled with a thermally conductive material, such as a metal or DAG (thermally conductive paste). During operation, heat from the transistor is dissipated through the heat sink. In various embodiments of the invention, the plug hole is formed using either an anisotropic plasma or wet etch.

Claims

1. An apparatus, comprising;

an active semiconductor layer;

a transistor formed in the active silicon layer;

a bulk silicon layer having a first surface and a second surface;

an oxide layer formed between the active silicon layer and the first surface of the bulk silicon layer; and

a heat sink formed in the bulk silicon layer and configured to sink heat sourced through the oxide layer to the second surface of the bulk silicon layer, the heat sink being a thermally conductive material provided in the bulk silicon layer, the thermally conductive material being a thermally conductive paste.

2. The apparatus of claim 1, wherein the transistor is an MOS transistor.

3. The apparatus of claim 1, wherein the transistor is a bipolar transistor.

4. The apparatus of claim 1, further comprising isolation regions formed around the transistor in the active silicon layer and contacting the oxide layer formed between the active silicon layer and the first surface of the bulk silicon layer.

5. The apparatus of claim 1, wherein the heat sink is substantially plug shaped.

6. The apparatus of claim 5, wherein the plug has a length substantially the same as the thickness of the bulk silicon layer.

7. The apparatus of claim 5, wherein the plug has a circumference ranging from 1 to 50000 microns.

8. The apparatus of claim 1, further comprising

a plurality of transistors formed in the active region, and

a plurality of heat sinks associated with the plurality of transistors respectively, each of the plurality of heat sinks formed in the bulk silicon layer configured to sink heat sourced in the oxide layer to the second surface of the bulk silicon layer, each of the heat sinks being plugged shaped and filled with the thermally conductive paste.

9. The apparatus of claim 7, wherein the plurality of transistors and the plurality of heat sinks are formed on a semiconductor die.

10. The apparatus of claim 8, wherein the plurality of transistors and the plurality of heat sinks are formed on a semiconductor wafer.

11. The apparatus of claim 1, wherein the bulk silicon layer is formed in a semiconductor material having one of the following orientations:

100, 111, or 110.

12. The apparatus of claim 1, wherein the active silicon layer is formed in a semiconductor material having one of the following orientations:

100, 111, or 110.

13. The apparatus of claim 1, wherein the thermally conductive paste is DAG.