Devices and methods with programmable logic and digital signal processing regions
First Claim
1. A programmable logic device comprising:
- a plurality of programmable logic regions;
a digital signal processing region having a plurality of configurable modes of operation, the digital signal processing region comprising;
a plurality of multiplier circuits that each have a multiplier output, anda digital signal processing circuit dedicated to receiving one or more of the multiplier outputs and comprising circuitry that applies a particular digital signal processing operation to the received multiplier outputs depending on a selected mode of operation; and
interconnect resources that interconnect the digital signal processing region to at least some of the programmable logic regions.
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Abstract
A programmable logic integrated circuit device (“PLD”) includes programmable logic and a dedicated (i.e., at least partly hard-wired) digital signal processing region for performing or at least helping to perform digital signal processing tasks that are unduly inefficient to implement in the more general-purpose programmable logic and/or that, if implemented in the programmable logic, would operate unacceptably or at least undesirably slowly. The digital signal processing region may include multiple digital signal processing stages. The digital signal processing region may include a multiplier stage and one ore more stages that can operate in combination with the multiplier stage. The digital signal processing region has a plurality of modes such as for providing multiply-and-accumulate operation, multiply-and-add operation, etc.
163 Citations
35 Claims
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1. A programmable logic device comprising:
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a plurality of programmable logic regions; a digital signal processing region having a plurality of configurable modes of operation, the digital signal processing region comprising; a plurality of multiplier circuits that each have a multiplier output, and a digital signal processing circuit dedicated to receiving one or more of the multiplier outputs and comprising circuitry that applies a particular digital signal processing operation to the received multiplier outputs depending on a selected mode of operation; and interconnect resources that interconnect the digital signal processing region to at least some of the programmable logic regions. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31)
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32. A programmable logic device comprising:
- a multiplier circuit operative to multiply two inputs to the multiplier circuit, wherein at least one of the two inputs to the multiplier circuit is statically and dynamically programmable to be signed or unsigned; and
at least one memory bit coupled to the multiplier circuit for statically controlling at least one of the two inputs to the multiplier circuit to be signed or unsigned. - View Dependent Claims (33)
- a multiplier circuit operative to multiply two inputs to the multiplier circuit, wherein at least one of the two inputs to the multiplier circuit is statically and dynamically programmable to be signed or unsigned; and
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34. A programmable logic device comprising:
- a multiplier circuit operative to multiply two inputs to the multiplier circuit, wherein at least one of the two inputs to the multiplier circuit is statically and dynamically programmable to be signed or unsigned; and
at least one dynamic signed/unsigned control input coupled to the multiplier circuit, wherein the at least one dynamic signed/unsigned control input recieves at least one corresponding control input signal for dynamically controlling at least one of the two inputs to the multiplier circuit to signed or unsigned.
- a multiplier circuit operative to multiply two inputs to the multiplier circuit, wherein at least one of the two inputs to the multiplier circuit is statically and dynamically programmable to be signed or unsigned; and
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35. A programmable logic device of comprising:
- a multiplier circuit operative to multiply two inputs to the multiplier circuit, wherein at least one of the two inputs to the multiplier circuit is statically and dynamically programmable to be signed or unsigned; and
at least one dynamic signed/unsigned control input coupled to the multiplier circuit, wherein the at least one register circuit for statically or dynamically controlling at least one of the two inputs to the multiplier circuit to be signed or unsigned.
- a multiplier circuit operative to multiply two inputs to the multiplier circuit, wherein at least one of the two inputs to the multiplier circuit is statically and dynamically programmable to be signed or unsigned; and
Specification