Single supply level converter

• US 7,119,578 B2
• Filed: 11/24/2003
• Issued: 10/10/2006
• Est. Priority Date: 11/24/2003
• Status: Active Grant

• Current Assignee: MediaTek, Inc.
• Original Assignee: International Business Machines Corporation
• Inventors: Correale, Anthony Jr., Joshi, Rajiv V., Puri, Ruchir, Kung, David S., Pan, Zhigang
• Primary Examiner(s): CHANG, DANIEL D
• Application Number:
  US10/720,466
• Publication Number:
  US 20050110519A1
• Time in Patent Office: 1,051 Days
• Field of Search: 326/68, 326 70- 72, 326/76, 326/81, 326/83, 326/86, 327/333
• US Class Current: 326/81
• CPC Class Codes: H03K 19/018521 of complementary type, e.g. CMOS
• CPC Class Codes: H03K 19/0948 using CMOS or complementary insulated gate field-effect transistors

Abstract

A level converter for interfacing two circuits supplied by different supply voltages, and integrated circuit including the level converter interfacing circuit in two different voltage islands. A first buffer is supplied by a virtual supply and receives an input signal from a lower voltage circuit. The first buffer drives a second buffer, which is supplied by a higher supply voltage. An output from the second buffer switches a supply select to selectively pass the higher supply voltage or a reduced supply voltage to the first buffer.

Claims

1. An integrated circuit (IC) comprising:

a plurality of circuit rows;

at least one low voltage island in at least one of said plurality of circuit rows, circuit elements in each said at least one low voltage island being powered by a low voltage (V_ddl) supply; and

at least one high voltage island in said at least one of said plurality of circuit rows, circuit elements in each said at least one high voltage island being powered by a high voltage (V_ddh) supply) V_ddh being a higher voltage than V_ddl; and

,

at least one level converter comprising;

a first buffer receiving an input signal from said at least one low voltage island, said first buffer being connected between a virtual supply and a supply return;

a second buffer receiving an output of said first buffer and connected between V_ddh and said supply return; and

a supply select between V_ddh and said virtual supply, said supply select receiving an output from said second buffer and selectively passing V_ddh or a reduced supply voltage to said virtual supply responsive to said output from said second buffer.

2. An IC as in claim 1, wherein said second buffer is an inverter.

3. An IC as in claim 1, wherein said supply select is a supply switch in parallel with at least one diode, both connected between said first supply and said virtual supply.

4. An IC converter as in claim 3, wherein said supply switch is a field effect transistor (FET) gated by said output of said second buffer and said at least one diode is a diode connected FET.

5. An IC as in claim 4, wherein said supply switch FET is a P-type FET (PFET) and said at least one diode connected FET an N-type FET (NFET) diode.

6. An IC as in claim 5, wherein said at least one diode connected NFET is a pair of series connected NFET diodes.

7. An IC as in claim 5, wherein said second buffer is a CMOS inverter.

8. An IC as in claim 7, wherein said first buffer is a CMOS inverter.

9. An IC as in claim 7, wherein said first buffer is a logic gate.

10. An IC as in claim 7, wherein said logic gate is a NAND gate receiving a plurality of V_ddl inputs.

11. An IC as in claim 7, wherein said CMOS inverter includes an NFET having a threshold higher than other NFETs in said level converter.

12. An IC as in claim 1, wherein said reduced supply voltage is below V_ddl.