Low-skew single-ended to differential converter

• US 7,119,602 B2
• Filed: 09/30/2004
• Issued: 10/10/2006
• Est. Priority Date: 09/30/2004
• Status: Expired due to Fees

• Current Assignee: Telefonaktiebolaget LM Ericsson
• Original Assignee: Koninklijke Philips Electronics N.V. (Koninklijke Philips N.V.)
• Inventors: Davis, Bradley Kendall
• Primary Examiner(s): Callahan, Timothy P.
• Assistant Examiner(s): COX, CASSANDRA F
• Application Number:
  US10/957,140
• Publication Number:
  US 20060066377A1
• Time in Patent Office: 740 Days
• Field of Search: None
• US Class Current: 327/415
• CPC Class Codes: G06F 1/10 Distribution of clock signals , e.g. skew

Abstract

A single-ended to differential converter uses a cross-coupled latch that maximizes the output zero-crossing symmetry and is self compensating over PVT variations. An in-phase driving signal is provided by an always-on transmission gate coupled to the input. An out-of-phase driving signal is provided by an inverter coupled to the input. The in-phase and out-of-phase driving signals each drive an input of the cross-coupled latch. The in-phase driving signal from the always-on transmission gate starts to bring the cross-coupled latch into conduction, and when the out-of-phase driving signal arrives, the simultaneous driving of the cross-coupled latch causes a rapid and symmetric transition of both outputs of the cross-coupled latch.

Claims

1. A single-ended to differential converter comprising:

an input stage that provides a first driving signal and a second driving signal from an input signal, the first and second driving signals being out-of-phase with each other, the input stage including;

a transmission gate, operably coupled to the input signal, that is configured to provide the first driving signal, the transmission gate being configured to be continuously enabled to propagate the input signal to the first driving signal, and

an input-stage inverter, operably coupled to the input signal, that is configured to provide the second driving signal, and

a cross-coupled latch, operably coupled to the first and second driving signals, and is configured to provide;

a first latched signal and

a second latched signal that is out-of-phase with the first latched signal.

2. The converter of claim 1, further including:

a first string of inverters, operably coupled to the first latched signal, that is configured to provide a lint output signal, and

a second string of inverters, operably coupled to the second latched signal, that is configured to provide a second output signal that is out-of-phase with the first output signal.

3. The convener of claim 2, further including

an input buffer that is configured to couple the input signal to the transmission gate and the input-stage inverter.

4. The converter of claim 2, wherein

the cross-coupled latch includes:

a first inverter wit an input coupled to the first driving signal and an output tat provides the first latched signal,

a second inverter with an input coupled to the second driving signal and an output tat provides the second latched signal,

wherein

the output of the first inverter is coupled to the input of the second inverter, and

the output of the second inverter is coupled to the input of the first inverter.

5. The converter of claim 2, wherein

each of the first and second string of inverters includes progressively larger transistors between the respective first and second latched signals and the first and second output signals.

6. The converter of claim 1, wherein

the cross-coupled latch includes:

a first inverter with an input coupled to the first driving signal and an output that provides the first latched signal,

a second inverter with an input coupled to the second driving signal and an output that provides the second latched signal,

wherein

the output of the first inverter is coupled to the input of the second inverter, and

the output of the second inverter is coupled to the input of the first inverter.

7. The converter of claim 6, wherein

the first and second inverters and the input stage are embodied using CMOS transistors.

8. The convener of claim 1, further including:

a first string of inverters, operably coupled to the first latched signal, that is configured to provide a first output signal, and

a second string of inverters, operably coupled to the second latched signal, that is configured to provide a second output signal tat is out-of-phase with the first output signal.

9. The convener of claim 8, wherein

the cross-coupled latch includes:

a first inverter with an input coupled to the first driving signal and an output that provides the first latched signal,

a second inverter with an input coupled to the second driving signal and an output that provides the second latched signal,

wherein

the output of the first inverter is coupled to the input of the second inverter, and

the output of the second inverter is coupled to the input of the first inverter.

10. The converter of claim 8, wherein

each of the first and second string of inverters includes progressively larger transistors between the respective first and second latched signals and the first and second output signals.