Dual-channel instrumentation amplifier

• US 7,119,612 B1
• Filed: 09/29/2004
• Issued: 10/10/2006
• Est. Priority Date: 01/05/2004
• Status: Active Grant

• Current Assignee: National Semiconductor Corporation (Texas Instruments, Inc.)
• Original Assignee: National Semiconductor Corporation (Texas Instruments, Inc.)
• Inventors: Wan, Jun, Holloway, Peter R.
• Primary Examiner(s): Nguyen, Khanh Van
• Application Number:
  US10/954,417
• Time in Patent Office: 741 Days
• Field of Search: 330/9, 330/253
• US Class Current: 330/9
• CPC Class Codes: H03F 1/02 Modifications of amplifiers to raise the efficiency, e.g. gliding Class A stages, use of an auxiliary oscillation
• CPC Class Codes: H03F 2200/261 Amplifier which being suitable for instrumentation applications
• CPC Class Codes: H03F 2200/78 A comparator being used in a controlling circuit of an amplifier
• CPC Class Codes: H03F 2203/45318 the AAC comprising a cross coupling circuit, e.g. two extra transistors cross coupled
• CPC Class Codes: H03F 2203/45521 the FBC comprising op amp stages, e.g. cascaded stages of the dif amp and being coupled between the LC and the IC
• CPC Class Codes: H03F 3/45179 using MOSFET transistors as the active amplifying circuit H03F3/45278 takes precedence
• CPC Class Codes: H03F 3/45188 Non-folded cascode stages
• CPC Class Codes: H03F 3/45475 using IC blocks as the active amplifying circuit
• CPC Class Codes: H03F 3/68 Combinations of amplifiers, e.g. multi-channel amplifiers for stereophonics power amplifiers using a combination of several semiconductor amplifiers H03F3/211; combinations of amplifiers using coupling networks with distributed constants H03F3/602

Abstract

A dual-channel instrumentation amplifier includes two channels of PMOS transistor differential pairs which are configured in a Y-connection and cross-coupled to two diode-connected NMOS transistors. Each input channel has a non-linear voltage-current characteristic. But when the differential currents cancel at the NMOS transistor diodes, both input channels have the same differential input voltage, regardless of any non-linearity. As thus configured, a high accuracy instrumentation amplifier which operates in current mode is realized with excellent DC matching and high common mode rejection ratio. In one embodiment, the dual-channel instrumentation amplifier is used as input stage for the linear comparator to enable the linear comparator to operate at a high rate of speed with excellent channel matching.

Claims

1. An instrumentation amplifier comprising:

a first differential pair of PMOS transistors coupled to receive first and second input signals at first and second input terminals, the first differential pair having common source terminals being biased by a first bias current, the drain terminal of the first PMOS transistor in the first differential pair being coupled to a first node and the drain terminal of the second PMOS transistor in the first differential pair being coupled to a second node;

a second differential pair of PMOS transistors coupled to receive third and fourth input signals at third and fourth input terminals, the second differential pair having common source terminals being biased by a second bias current, the drain terminal of the first PMOS transistor in the second differential pair being coupled to the first node and the drain terminal of the second PMOS transistor in the second differential pair being coupled to the second node;

a first diode connected NMOS transistor having gate and drain terminals coupled to the first node and a source terminal coupled to a first power supply voltage; and

a second diode connected NMOS transistor having gate and drain terminals coupled to the second node and a source terminal coupled to the first power supply voltage,

wherein the difference between the first and second input signals forms a first input voltage and the difference between the third and fourth input signals forms a second input voltage, the first node provides a first differential output voltage and the second node provides a second differential output voltage such that the first and second differential output voltages are indicative of a difference between the first input voltage and the second input voltage.

2. The instrumentation amplifier of claim 1, wherein a current flowing into the first node has a positive value when the first input voltage is greater than the second input voltage and the current has a negative value when the first input voltage is less than the second input voltage.

3. The instrumentation amplifier of claim 1, wherein the first bias current is equal to the second bias current.

4. The instrumentation amplifier of claim 1, wherein the PMOS transistors in each of the first and second differential pairs are of the same size and the first diode connected NMOS transistor and the second diode connected NMOS transistor are of the same size.

5. The instrumentation amplifier of claim 1, further comprising:

a first reset switch coupled between the first and second input terminals of the first differential pair; and

a second reset switch coupled between the third and fourth input terminals of the second differential pair,

wherein the first reset switch and the second rest switch are closed during reset operations to reset the instrumentation amplifier.

6. The instrumentation amplifier of claim 1, wherein the first bias current is provided by a first current source coupled between a second power supply voltage and the common source terminals of the first differential pair and the second bias current is provided by a second current source coupled between the second power supply voltage and the common source terminals of the second differential pair.

7. The instrumentation amplifier of claim 6, wherein the first current source comprises a first current mirror for mirroring a current generated by a third current source having constant or near constant temperature coefficient and the second current source comprises a second current mirror for mirroring the current generated by the third current source having constant or near constant temperature coefficient.

8. The instrumentation amplifier of claim 1, wherein the first and second input signals comprise first and second switching voltage reference signals having opposite phase, the third input signal comprises the first switching voltage reference signal and the fourth input signal comprises a voltage ramp signal.

9. A linear comparator comprising:

a dual-channel instrumentation amplifier input stage, each channel of the instrumentation amplifier input stage comprising a pair of differential input terminals receiving a pair of input signals, the dual-channel instrumentation amplifier input stage providing first and second differential output voltages;

a differential to single ended pre-amplifier coupled to receive the first and second differential output voltages from the dual-channel instrumentation amplifier input stage and providing a third output voltage; and

a low impedance high gain clipping pre-amplifier coupled to receive the third output voltage and provide a fourth output voltage,

wherein a first pair of input signals are coupled to a first input channel of the instrumentation amplifier to provide a first input voltage and a second pair of input signals are coupled to a second input channel of the instrumentation amplifier to provide a second input voltage, the fourth output voltage being indicative of a high gain multiplication of the difference between the first input voltage and the second input voltage.

10. The linear comparator of claim 9, wherein the dual-channel instrumentation amplifier input stage comprises:

a first differential pair of PMOS transistors coupled to receive first and second input signals at first and second input terminals, the first differential pair having common source terminals being biased by a first bias current, the drain terminal of the first PMOS transistor in the first differential pair being coupled to a first node and the drain terminal of the second PMOS transistor in the first differential pair being coupled to a second node;

a second differential pair of PMOS transistors coupled to receive third and fourth input signals at third and fourth input terminals, the second differential pair having common source terminals being biased by a second bias current, the drain terminal of the first PMOS transistor in the second differential pair being coupled to the first node and the drain terminal of the second PMOS transistor in the second differential pair being coupled to the second node;

a first diode connected NMOS transistor having gate and drain terminals coupled to the first node and a source terminal coupled to a first power supply voltage; and

a second diode connected NMOS transistor having gate and drain terminals coupled to the second node and a source terminal coupled to the first power supply voltage,

wherein the difference between the first and second input signals forms a first input voltage and the difference between the third and fourth input signals forms a second input voltage, the first node provides a first differential output voltage and the second node provides a second differential output voltage such that the first and second differential output voltages are indicative of a difference between the first input voltage and the second input voltage.

11. The linear comparator of claim 10, wherein a current flowing into the first node has a positive value when the first input voltage is greater than the second input voltage and the current has a negative value when the first input voltage is less than the second input voltage.

12. The linear comparator of claim 10, wherein the first bias current is equal to the second bias cent.

13. The linear comparator of claim 10, wherein the PMOS transistors in each of the first and second differential pairs are of the same size and the first diode connected NMOS transistor and the second diode connected NMOS transistor are of the same size.

14. The linear comparator of claim 10, further comprising:

a first reset switch coupled between the first and second input terminals of the first differential pair; and

a second reset switch coupled between the third and fourth input terminals of the second differential pair,

wherein the first reset switch and the second rest switch are closed during reset operations to reset the instrumentation amplifier.

15. The linear comparator of claim 10, wherein the first and second input signals comprise first and second switching voltage reference signals having opposite phase, the third input signal comprises the first switching voltage reference signal and the fourth input signal comprises a voltage ramp signal, and wherein the fourth output voltage being a switching output signal for used as a clock signal.