Off-chip LC circuit for lowest ground and VDD impedance for power amplifier

• US 7,119,631 B2
• Filed: 05/12/2004
• Issued: 10/10/2006
• Est. Priority Date: 03/12/2004
• Status: Expired due to Fees

• Current Assignee: Avago Technologies General IP PTE Limited (Broadcom, Inc.)
• Original Assignee: Broadcom Corporation (Broadcom, Inc.)
• Inventors: Li, Qiang (Tom), Castaneda, Jesus Alfonso
• Primary Examiner(s): Pascal, Robert
• Assistant Examiner(s): Glenn, Kimberly E
• Application Number:
  US10/844,237
• Publication Number:
  US 20050200426A1
• Time in Patent Office: 881 Days
• Field of Search: 330/302, 330/305, 330/307, 330/32, 330/33
• US Class Current: 333/32
• CPC Class Codes: H03F 1/565 using inductive elements
• CPC Class Codes: H03F 2200/09 A balun, i.e. balanced to or from unbalanced converter, being present at the output of an amplifier
• CPC Class Codes: H03F 2200/294 the amplifier being a low noise amplifier [LNA]
• CPC Class Codes: H03F 2200/372 Noise reduction and elimination in amplifier
• CPC Class Codes: H03F 3/195 in integrated circuits
• CPC Class Codes: H03F 3/24 of transmitter output stages
• CPC Class Codes: H03H 7/38 Impedance-matching networks

Abstract

Off-chip LC circuit for lowest ground and VDD impedance for power amplifier. A novel approach is made by which a chip to PCB (Printer Circuit Board) interface may be made such that the ground and VDD potential levels are effectively brought onto the die of the chip such that a true ground potential is maintained within the chip. This off-chip LC circuit operates cooperatively with an on-chip decoupling capacitor to reduce the overall effective inductance of the bond wires employed to bring signal and voltage levels from the die to the chip exterior. This circuit ensures a relatively low impedance for a PA (Power Amplifier) that is implemented within chip thereby providing for improved performance.

Claims

1. An off-chip LC (inductance-capacitance) circuit that communicatively couples to an integrated circuit, the circuit comprising:

a first RF (Radio Frequency) choke that communicatively couples an off-chip supply potential node to a first pin of the integrated circuit;

wherein the first pin connects to an on-chip supply potential node of a die that is implemented within the integrated circuit;

wherein the on-chip supply potential node powers an on-chip PA (Power Amplifier) that is implemented within the die;

a second RF choke that communicatively couples an off-chip ground potential node to a second pin of the integrated circuit;

wherein the second pin connects to an on-chip ground potential node of the die;

wherein the on-chip ground potential node serves as an on-chip ground reference of the on-chip PA;

an off-chip joining capacitor whose ends communicatively couple to each of the first pin and the second pin of the integrated circuit; and

an off-chip tuning capacitor whose ends communicatively couple to the first pin of the integrated circuit and an off-chip true ground potential node.

2. The circuit of claim 1, wherein:

the integrated circuit includes an on-chip decoupling capacitor whose ends communicatively couple to the on-chip supply potential node and the on-chip ground potential node.

3. The circuit of claim 1, wherein:

the first pin connects to the on-chip supply potential node of the die via a first bond wire;

the second pin connects to the on-chip ground potential node of the die via a second bond wire;

a third pin of the integrated circuit connects to an output of the on-chip PA via a third bond wire;

a first interface from an exterior of the integrated circuit to the die of the integrated circuit that includes the first pin and the first bond wire is characterized by a first PBWM (Package Bond Wire Model) having a first impedance;

a second interface from the exterior of the integrated circuit to the die of the integrated circuit that includes the second pin and the second bond wire is characterized by a second PBWM having a second impedance; and

a third interface from the exterior of the integrated circuit to the die of the integrated circuit that includes the third pin and the third bond wire is characterized by a third PBWM having a third impedance.

4. The circuit of claim 3, wherein:

the third pin is communicatively coupled to an antenna.

5. The circuit of claim 3, wherein:

the integrated circuit includes an on-chip decoupling capacitor whose ends communicatively couple to the on-chip supply potential node and the on-chip ground potential node; and

the on-chip decoupling capacitor and the off-chip joining capacitor operate cooperatively to reduce an effective inductance associated with each of the first PBWM and the second PBWM.

6. The circuit of claim 3, wherein:

a capacitance value of the off-chip tuning capacitor is selected such that the capacitive-related impedance corresponding to the off-chip tuning capacitor substantially cancels a parallel combination of the first impedance and the second impedance that correspond to the first PBWM and the second PBWM, respectively.

7. The circuit of claim 1, wherein:

the first RF choke substantially blocks any AC (Alternating Current) signal from being transmitted between the off-chip supply potential node and the first pin; and

the second RF choke substantially blocks any AC signal from being transmitted between the off-chip ground potential node and the second pin.

8. The circuit of claim 1, wherein:

the first RF choke operates as a short circuit with respect to any DC (Direct Current) signal being transmitted between the off-chip supply potential node and the first pin; and

the second RF choke operates as a short circuit with respect to any DC signal being transmitted between the off-chip ground potential node and the second pin.

9. The circuit of claim 1, wherein:

the off-chip tuning capacitor and the off-chip joining capacitor cooperatively provide a shunt path to dissipate for any AC (Alternating Current) signal existent at either of the first pin or the second pin.

10. The circuit of claim 1, wherein:

the integrated circuit is implemented within a communication device that supports wireless communication according to at least one of an IEEE (Institute of Electrical &

Electronics Engineers) 802.11b standard and an IEEE 802.15.1 BLUETOOTH®

core.

11. An off-chip LC (inductance-capacitance) circuit that communicatively couples to an integrated circuit, the circuit comprising:

a first RF (Radio Frequency) choke that communicatively couples an off-chip supply potential node to a first pin of the integrated circuit;

wherein the first pin connects to an on-chip supply potential node of a die that is implemented within the integrated circuit;

wherein the on-chip supply potential node powers an on-chip PA (Power Amplifier) that is implemented within the die;

a second RF choke that communicatively couples an off-chip ground potential node to a second pin of the integrated circuit;

wherein the second pin connects to an on-chip ground potential node of the die;

wherein the on-chip ground potential node serves as an on-chip ground reference of the on-chip PA;

an off-chip joining capacitor whose ends communicatively couple to each of the first pin and the second pin of the integrated circuit;

an off-chip tuning capacitor whose ends communicatively couple to the first pin of the integrated circuit and an off-chip true ground potential node;

wherein the integrated circuit includes an on-chip decoupling capacitor whose ends communicatively couple to the on-chip supply potential node and the on-chip ground potential node;

wherein the first pin connects to the on-chip supply potential node of the die via a first bond wire;

wherein the second pin connects to the on-chip ground potential node of the die via a second bond wire;

a third pin of the integrated circuit connects to an output of the on-chip PA via a third bond wire;

a first interface from an exterior of the integrated circuit to the die of the integrated circuit that includes the first pin and the first bond wire is characterized by a first PBWM (Package Bond Wire Model) having a first impedance;

a second interface from the exterior of the integrated circuit to the die of the integrated circuit that includes the second pin and the second bond wire is characterized by a second PBWM having a second impedance; and

a third interface from the exterior of the integrated circuit to the die of the integrated circuit that includes the third pin and the third bond wire is characterized by a third PBWM having a third impedance.

12. The circuit of claim 11, wherein:

the on-chip decoupling capacitor and the off-chip joining capacitor operate cooperatively to reduce an effective inductance associated with each of the first PBWM and the second PBWM.

13. The circuit of claim 11, wherein:

a capacitance value of the off-chip tuning capacitor is selected such that the capacitive-related impedance corresponding to the off-chip tuning capacitor substantially cancels a parallel combination of the first impedance and the second impedance that correspond to the first PBWM and the second PBWM, respectively.

14. The circuit of claim 11, wherein:

the first RF choke substantially blocks any AC (Alternating Current) signal from being transmitted between the off-chip supply potential node and the first pin;

the second RF choke substantially blocks any AC signal from being transmitted between the off-chip ground potential node and the second pin;

the first RF choke operates as a short circuit with respect to any DC (Direct Current) signal being transmitted between the off-chip supply potential node and the first pin;

the second RF choke operates as a short circuit with respect to any DC signal being transmitted between the off-chip ground potential node and the second pin; and

the off-chip tuning capacitor and the off-chip joining capacitor cooperatively provide a shunt path to dissipate for any AC (Alternating Current) signal existent at either of the first pin or the second pin.

15. The circuit of claim 11, wherein:

the integrated circuit is implemented within a communication device that supports wireless communication according to at least one of an IEEE (Institute of Electrical &

Electronics Engineers) 802.11b standard and an IEEE 802.15.1 BLUETOOTH®

core.

16. A method for providing a lowest ground potential and an off-chip supply potential impedance to an on-chip PA (Power Amplifier), the method comprising:

providing an off-chip joining capacitor and an on-chip decoupling capacitor to reduce an overall effective inductance of a parallel combination of a first PBWM (Package Bond Wire Model) and a second PBWM;

wherein the first PBWM characterizes a first interface from an exterior of an integrated circuit to a die of the integrated circuit that includes a first pin and a first bond wire;

wherein the second PBWM characterizes a second interface from the exterior of the integrated circuit to the die of the integrated circuit that includes a second pin and a second bond wire;

providing an off-chip tuning capacitor to provide a shunt path to dissipate any AC (Alternating Current) signal existent at either of the first pin or the second pin;

providing a first RF (Radio Frequency) choke to operate as a short circuit with respect to any DC (Direct Current) signal being transmitted between an off-chip supply potential node and the first pin that is communicatively coupled thereto via the first RF choke; and

providing a second RF choke to operate as a short circuit with respect to any DC signal being transmitted between an off-chip ground potential node and the second pin that is communicatively coupled thereto via the second RF choke.

17. The method of claim 16, further comprising:

selecting a capacitance value of the off-chip tuning capacitor such that the capacitive-related impedance corresponding to the off-chip tuning capacitor substantially cancels a parallel combination of a first impedance and a second impedance that correspond to the first PBWM and the second PBWM, respectively.

18. The method of claim 16, wherein

the first RF choke substantially blocks any AC (Alternating Current) signal from being transmitted between the off-chip supply potential node and the first pin;

and

the second RF choke substantially blocks any AC signal from being transmitted between the off-chip ground potential node and the second pin.

19. The method of claim 16, wherein:

the first RF choke operates as a short circuit with respect to any DC (Direct Current) signal being transmitted between the off-chip supply potential node and the first pin; and

the second RF choke operates as a short circuit with respect to any DC signal being transmitted between the off-chip ground potential node and the second pin.

20. The method of claim 16, wherein:

the method is performed within a communication device that supports wireless communication according to at least one of an IEEE (Institute of Electrical &

Electronics Engineers) 802.11b standard and an IEEE 802.15.1 BLUETOOTH®

core.