Integrated transformer

• US 7,119,650 B2
• Filed: 08/05/2004
• Issued: 10/10/2006
• Est. Priority Date: 11/23/1999
• Status: Expired due to Fees

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Gardner, Donald S.
• Primary Examiner(s): Nguyen, Tuyen T
• Application Number:
  US10/913,615
• Publication Number:
  US 20050017837A1
• Time in Patent Office: 796 Days
• Field of Search: 336/65, 336/83, 336/200, 336206-208, 336/232, 257/258, 257/421, 257/528, 257/531, 296/021
• US Class Current: 336/200
• CPC Class Codes: H01F 17/0006 Printed inductances printed coils for dynamo-electric machines H02K3/26; printed circuits H05K
• CPC Class Codes: H01F 2017/0046 with a conductive path having a bridge
• CPC Class Codes: H01F 2017/008 Electric or magnetic shielding of printed inductances
• CPC Class Codes: H01F 41/042 by thin film techniques
• CPC Class Codes: H01F 41/046 structurally combined with ferromagnetic material
• CPC Class Codes: H01L 23/522 including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
• CPC Class Codes: H01L 23/5227 Inductive arrangements or effects of, or between, wiring layers other inductive arrangements H01L23/645
• CPC Class Codes: H01L 23/552 Protection against radiation, e.g. light or electromagnetic waves
• CPC Class Codes: H01L 23/645 Inductive arrangements H01L23/647, H01L23/66 take precedence
• CPC Class Codes: H01L 27/08 including only semiconductor components of a single kind
• CPC Class Codes: H01L 28/10 Inductors
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H01L 2924/09701 Low temperature co-fired ceramic [LTCC]
• CPC Class Codes: Y10T 29/4902 Electromagnet, transformer or inductor

Abstract

A transformer comprises a first inductor and a second inductor. The first inductor has one or more trenches and comprises a first conductor defining a signal path along the one or more trenches of the first inductor. The second inductor has one or more trenches and comprises a second conductor defining a signal path along the one or more trenches of the second inductor.

Claims

1. A method, comprising:

forming a first inductor in a first dielectric layer over a substrate, the first inductor having an at least one trench, the at least one trench having a pair of walls and a bottom;

forming a first conductor over the first inductor, the first conductor defining a first signal path along the pair of walls and the bottom of the dielectric layer;

forming a first magnetic layer over the dielectric layer, the first magnetic layer defining a second signal path parallel to the first signal path;

forming a second inductor in the dielectric layer over the substrate, the second inductor having an at least one trench, the at least one trench having a pair of walls and a bottom;

forming a second conductor over the second inductor, the second conductor defining a third signal path along the pair of walls and the bottom of the dielectric layer;

forming a second magnetic layer over the dielectric layer, the second magnetic layer defining a fourth signal path parallel to the third signal path.

2. The method of claim 1, wherein forming the first conductor comprises forming the first signal path along a first leg and a second leg of the first conductor and forming the third signal path along a third leg of the second conductor, wherein the third leg is positioned between the first leg and the second leg of the first conductor.

3. The method of claim 2, further comprising tapping a voltage potential from the second conductor on the third leg.

4. The method of claim 1, wherein the first conductor is positioned alongside the second conductor.

5. The method of claim 1, wherein forming the first magnetic layer and the second magnetic layer comprises forming the first magnetic layer and the second magnetic layer from an amorphous cobalt alloy.

6. The method of claim 1, wherein a second dielectric layer is formed over the first conductor and under the first magnetic layer.

7. The method of claim 1, wherein a third dielectric layer is formed over the second conductor and under the second magnetic layer.