Die anti-tampering sensor
First Claim
1. A die anti-tampering sensor for protecting against tampering of integrated circuits comprising:
- a metal wire loop located in a metallization layer above said integrated circuits,a semiconductor load device which charges said metal wire loop to a logical ‘
1’
level,a multiplicity of semiconductor devices which discharge said metal wire loop to a logical ‘
0’
level at certain periodic times,a NAND logic gate, with logic inputs, placed among said integrated circuits,a multiplicity of vias connecting a multiplicity of points along said metal wire loop down to said inputs of said NAND logic gate within said integrated circuit,a multiplicity of vias connecting a multiplicity of points along said metal wire loop down to said semiconductor devices which discharge said metal wire loop to a logical ‘
0’
level at certain periodic times, andan output of said NAND logic gate which goes to a logic ‘
1’ and
activates an alarm and security action whenever any one of said NAND inputs goes to logical ‘
0’
.
3 Assignments
0 Petitions
Accused Products
Abstract
This sensor circuit and method for defending against tampering with an integrated circuit die uses metal wire loops to protect the circuitry. In addition, these metal wire loops have several via pairs along its length. One of the vias of the via pair goes to a NAND gate which detects a break in a section of a metal wire loop. A second via of the via pair is used to periodically discharge a metal wire loop to remove residual charge, in preparation for charging the metal wire loop and detecting any uncharged section. A given integrated circuit can have one or more metal wire loops on top of the circuitry to be protected. Each metal wire loop has one or more NAND gates. These outputs of the NAND gates can be fed into OR gates to produce an overall signal which activates an alarm or other security action such as erasure of electrically erasable programmable read only memory (EEPROM).
13 Citations
40 Claims
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1. A die anti-tampering sensor for protecting against tampering of integrated circuits comprising:
-
a metal wire loop located in a metallization layer above said integrated circuits, a semiconductor load device which charges said metal wire loop to a logical ‘
1’
level,a multiplicity of semiconductor devices which discharge said metal wire loop to a logical ‘
0’
level at certain periodic times,a NAND logic gate, with logic inputs, placed among said integrated circuits, a multiplicity of vias connecting a multiplicity of points along said metal wire loop down to said inputs of said NAND logic gate within said integrated circuit, a multiplicity of vias connecting a multiplicity of points along said metal wire loop down to said semiconductor devices which discharge said metal wire loop to a logical ‘
0’
level at certain periodic times, andan output of said NAND logic gate which goes to a logic ‘
1’ and
activates an alarm and security action whenever any one of said NAND inputs goes to logical ‘
0’
. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20)
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21. A method of protecting against tampering of integrated circuits comprising the steps of:
-
locating a metal wire loop in a metallization layer above said integrated circuits, charging said metal wire loop to a logical ‘
1’
level with a semiconductor load device,discharging said metal wire loop to a logical ‘
0’
level at certain periodic times with a multiplicity of semiconductor devices,placing a NAND logic gate, with logic inputs, among said integrated circuits, connecting a multiplicity of points along said metal wire loop down to said inputs of said NAND logic gate within said integrated circuit with a multiplicity of vias, connecting a multiplicity of points along said metal wire loop down to said semiconductor devices which discharge said metal wire loop to a logical ‘
0’
level at certain periodic times with a multiplicity of vias, andactivating an alarm and security action whenever any one of said NAND inputs goes to logical ‘
0’
causing the output of said NAND logic gate go to a logic ‘
1’
. - View Dependent Claims (22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, 35, 36, 37, 38, 39, 40)
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Specification