Apparatus and manufacture method for flat display

• US 7,119,857 B1
• Filed: 09/22/2000
• Issued: 10/10/2006
• Est. Priority Date: 09/24/1999
• Status: Expired due to Term

• Current Assignee: Japan Display Central Incorporated (Japan Display Incorporated)
• Original Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Inventors: Hanazawa, Yasuyuki, Nakamura, Takafumi
• Primary Examiner(s): Nguyen, Dung T.
• Application Number:
  US09/667,566
• Time in Patent Office: 2,209 Days
• Field of Search: 349 38- 43, 349/143, 349/54, 349/139
• US Class Current: 349/38
• CPC Class Codes: G02F 1/136213 Storage capacitors associated with the pixel electrode
• CPC Class Codes: G02F 1/136259 Repairing; Defects
• CPC Class Codes: G02F 1/136286 Wiring, e.g. gate line, drain line
• CPC Class Codes: H01L 27/124 with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits wiring structures per se H01L23/52
• CPC Class Codes: H01L 27/1255 integrated with passive devices, e.g. auxiliary capacitors

Abstract

There is disclosed a method of manufacturing a flat display in which a switching element (TFT) having caused a display pixel defect can securely be repaired. The flat display of the present invention is formed by forming a semiconductor layer and an auxiliary capacity electrode in the same layer on a glass substrate, forming a gate insulating film on a top surface, forming a gate electrode and an auxiliary capacity feeder in the same layer on the top surface, forming an interlayer insulating film on a top surface, and forming a source electrode and drain electrode on a top surface. Since a wiring portion between the auxiliary capacity electrode and the pixel electrode is irradiated with laser to increase the resistance of a wiring portion, the pixel electrode fails to be influenced by a voltage of the auxiliary capacity feeder, occurrence of the display pixel defect can be reduced, and manufacture yield can be enhanced.

Claims

1. A flat display provided with an array substrate having an upper side and a lower side, the array substrate comprising:

signal lines and scanning lines longitudinally and transversely arranged on an insulating substrate;

a plurality of pixel electrodes connected to respective intersections of said signal lines and said scanning lines via switching elements;

a plurality of auxiliary capacity electrodes electrically connected to said switching elements; and

an auxiliary capacity feeder disposed opposite to said auxiliary capacity electrode via an insulating layer, said flat display comprising;

a first wiring layer electrically connected to said auxiliary capacity electrode;

a second wiring layer electrically connected to source electrodes of said switching elements and said first wiring layer; and

a third wiring layer electrically connected to said pixel electrode and the source electrodes of said switching elements,

wherein said first wiring layer is formed on a layer closer to the lower side of the array substrate than the second wiring layer and the second wiring layer is formed on a layer closer to the upper side of the array substrate than the first wiring layer, and a length of said first wiring layer is set to be equal to that of the second wiring layer.

2. The flat display according to claim 1 wherein said second wiring layer and said auxiliary capacity feeder are formed not to be vertically superposed onto each other.

3. The flat display according to claim 1 wherein said first wiring layer is formed on the same layer as that of said auxiliary capacity electrode.

4. The flat display according to claim 1 wherein said second and third wiring layers are formed on the same layer.

5. The flat display according to claim 1 wherein a channel area of said switching element, said auxiliary capacity electrode and said first wiring layer are formed using polycrystalline silicon.

6. The flat display of claim 1, wherein:

the switching elements each include a gate, a drain, and the source electrode.