Method for evaluation of reticle image using aerial image simulator

• US 7,120,285 B1
• Filed: 02/29/2000
• Issued: 10/10/2006
• Est. Priority Date: 02/29/2000
• Status: Expired due to Term

• Current Assignee: GlobalFoundries, Inc.
• Original Assignee: Advanced Micro Devices, Inc.
• Inventors: Spence, Christopher A.
• Primary Examiner(s): WERNER, BRIAN P
• Application Number:
  US09/515,348
• Time in Patent Office: 2,415 Days
• Field of Search: 352/144, 352/145, 352/149, 352/151
• US Class Current: 382/144
• CPC Class Codes: G03F 1/70 Adapting basic layout or design of masks to lithographic process requirements, e.g., second iteration correction of mask patterns for imaging

Abstract

A method of evaluating a wafer structure formation process includes extracting the outline of an actual mask pattern, and simulating a lithographic process using the actual mask pattern to obtain a simulated wafer structure. The extracting the outline of the actual mask pattern may include, for example, imaging the actual mask using a scanning electron microscope (SEM). A second simulated wafer structure may also be obtained, by simulating the lithographic process using the ideal mask pattern design that was used in producing the actual mask pattern. Thus the relative contribution of mask pattern effects to overall wafer proximity effects may be evaluated by comparing the two simulated wafer structures, either with each other or against a benchmark such as a desired, ideal structure. This information may then be used to generate optical proximity correction (OPC) mask designs which compensate for mask patterning errors and give better wafer performance. The simulated wafer structures may be overlaid upon one another to allow for a direct comparison and full analysis of CD variations.

Claims

1. A method of analyzing a mask manufacturing process, the method comprising:

imaging at least a portion of a mask to be used in a wafer structure formation process;

simulating lithographic processing using data received from or derived from the imaging of the portion of the mask, thereby obtaining a first simulated wafer structure;

simulating lithographic processing using mask design data corresponding to the imaged portion of the mask as an input, thereby obtaining a second simulated wafer structure;

comparing the first simulated wafer structure to the second simulated wafer structure;

comparing the first and second simulated wafer structures to an ideal wafer structure representing the desired structure on a fabricated wafer to be transferred by the mask; and

based on the comparing steps, evaluating critical dimension variations across the wafer structure.

2. The method of claim 1, where first and second simulated wafer structures are obtained by the same simulation method.

3. The method of claim 1, where first and second simulated wafer structures are obtained by aerial image simulation.

4. The method of claim 1, where first and second simulated wafer structures are obtained by different simulation methods.

5. The method of claim 1, further comprising displaying the first simulated wafer structure on a display screen.

6. The method of claim 5, further comprising displaying the second simulated wafer structure on the display screen, wherein the first and second simulated wafer structures at least partially overlap with one another.

7. The method of claim 6, providing a user an option of selecting a figure of merit (FOM) by which critical dimension variations between the simulated wafer structures are to be calculated.

8. The method of claim 7, wherein the FOM is a line width.

9. The method of claim 7, wherein the FOM is a percentage difference in overall area of the first and second simulated structures.

10. The method of claim 1, wherein the imaging includes using a scanning electron microscope (SEM) to obtain an SEM image.

11. The method of claim 10, further comprising transforming the SEM image into computer-readable data.

12. The method of claim 11, wherein the transforming includes applying an image analysis algorithm to the image data.

13. The method of claim 11, further comprising scaling the data.

14. The method of claim 1, further comprising transforming data of a first type, obtained in the imaging, into data of a second type, to be used in the simulating.

15. The method of claim 1, wherein the simulating includes aerial simulation using a computer program.

16. The method of claim 15, wherein the simulating also includes simulating the developed resist image.

17. The method of claim 1, wherein the simulating includes simulating using an aerial image microscope system.

18. The method of claim 1, further comprising forming at least one of the first and second simulated wafer structures at various stages of the wafer structure formation process, and overlaying all of the simulated wafer structures on a display screen.

19. The method of claim 1, further comprising determining a location of greatest critical dimension variation between the first and second simulated wafer structures.