Reconfigurable memory module and method
First Claim
Patent Images
1. A memory module, comprising:
- a plurality of memory devices arranged in four ranks; and
a memory hub coupled to the memory devices in each of the ranks, the memory hub being programmable to configure the memory module in each of a plurality of modes, the memory hub being structured to simultaneously address all four ranks of memory devices in a first mode to simultaneously couple data to or from all of the memory devices in the memory module, to simultaneously address two ranks of memory devices in a second mode to simultaneously couple data to or from the memory devices in the two addressed ranks, or to address one rank of memory devices in a third mode to couple data to or from the memory devices in the addressed rank.
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Abstract
A computer system includes a controller coupled to a plurality of memory modules each of which includes a memory hub and a plurality of memory devices divided into a plurality of ranks. The memory hub is operable to configure the memory module to simultaneously address any number of ranks to operate in a high bandwidth mode, a high memory depth mode, or any combination of such modes.
467 Citations
61 Claims
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1. A memory module, comprising:
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a plurality of memory devices arranged in four ranks; and a memory hub coupled to the memory devices in each of the ranks, the memory hub being programmable to configure the memory module in each of a plurality of modes, the memory hub being structured to simultaneously address all four ranks of memory devices in a first mode to simultaneously couple data to or from all of the memory devices in the memory module, to simultaneously address two ranks of memory devices in a second mode to simultaneously couple data to or from the memory devices in the two addressed ranks, or to address one rank of memory devices in a third mode to couple data to or from the memory devices in the addressed rank. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10)
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11. A memory system, comprising:
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a controller operable to receive a memory request and to transmit a corresponding memory request to an input/output port; a plurality of memory modules, each of the memory modules comprising; a plurality of memory devices arranged in four ranks; and a memory hub operable to receive a memory request at an input/output port, the memory hub being coupled to the memory devices in each of the ranks, the memory hub being programmable to configure the memory module in a plurality of modes, the memory hub being structured to simultaneously address all four ranks of memory devices in a first mode to simultaneously couple data to or from all of the memory devices in the memory module, to simultaneously address two ranks of memory devices in a second mode to simultaneously couple data to or from the memory devices in the two addressed ranks, or to address one rank of memory devices in a third mode to couple data to or from the memory devices in the addressed rank; and a communications link coupling the input/output port of the controller to the input/output ports of the memory hubs in the respective memory modules. - View Dependent Claims (12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23)
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24. A computer system, comprising:
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a central processing unit (“
CPU”
);a system controller coupled to the CPU, the system controller being operable to receive a memory request from the central processing unit and to transmit a corresponding memory request to an input/output port; an input device coupled to the CPU through the system controller; an output device coupled to the CPU through the system controller; a storage device coupled to the CPU through the system controller; a plurality of memory modules, each of the memory modules comprising; a plurality of memory devices arranged in four ranks; and a memory hub operable to receive a memory request at an input/output port, the memory hub being coupled to the memory devices in each of the ranks, the memory hub being programmable to configure the memory module in a plurality of modes, the memory hub being structured to simultaneously address all of four ranks of memory devices in a first mode to simultaneously couple data to or from all of the memory devices in the memory module, to simultaneously address two ranks of memory devices in a second mode to simultaneously couple data to or from the memory devices in the two addressed ranks, or to address one rank of memory devices in a third mode to couple data to or from the memory devices in the addressed rank; and a communications link coupling the input/output port of the system controller to the input/output ports of the memory hubs in the respective memory modules. - View Dependent Claims (25, 26, 27, 28, 29, 30, 31, 32, 33, 34, 35, 36)
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37. A method of accessing data in a memory module containing a plurality of memory devices, the method comprising:
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dividing the memory devices into M ranks, where M is a positive greater than or equal to four; configuring the memory module to access the data stored in the memory module in a first data format in which M ranks of memory devices are simultaneously accessed; configuring the memory module to access the data stored in the memory module in a second data format in which M/2 ranks of memory devices are simultaneously accessed; and configuring the memory module to access the data stored in the memory module in a third data format in which one rank of memory devices is simultaneously accessed. - View Dependent Claims (38, 39, 40, 41, 42)
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43. In a computer system, a method of accessing data in a plurality of memory modules each of which contains a plurality of memory devices, the method comprising:
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dividing the memory devices in each of the memory modules into a plurality of ranks; configuring each of the memory modules to access the data stored in the memory module in one of a plurality of data formats each corresponding to a respective number of ranks of memory devices that are simultaneously accessed, a first of the memory modules being configured so that all of the ranks of memory devices in the first memory module are simultaneously addressed, a second of the memory modules being configured so that half of the ranks of memory devices in the second memory module are simultaneously addressed, and a third of the memory modules being configured so that each of the ranks of memory devices in the third memory module are individually addressed; and accessing data in each of the memory modules in the configured data format. - View Dependent Claims (44, 45, 46, 47, 48)
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49. A memory module, comprising:
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a plurality of memory devices arranged in a plurality of M ranks each having an N-bit data bus, the memory devices being operable to read or write data at a rate of X bits per second; and a memory hub coupled to the memory devices in each of the ranks, the memory hub being programmable to configure the memory module in a plurality of data formats each corresponding to a respective number of ranks of memory devices that are simultaneously accessed, the memory hub further including an N*P-bit input/output port that is operable to receive or transmit M*N data bits in N*P-bit words at a rate of (M*X)/P data words per second, where N and P are respective positive integers. - View Dependent Claims (50, 51, 52)
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53. A memory system, comprising:
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a controller operable to receive a memory request and to transmit a corresponding memory request to an input/output port; a plurality of memory modules, each of the memory modules comprising; a plurality of memory devices arranged in a plurality of M ranks each having an N-bit data bus, the memory devices being operable to read or write data at a rate of X bits per second; a memory hub coupled to the memory devices in each of the ranks, the memory hub being programmable to configure the memory module in a plurality of data formats each corresponding to a respective number of ranks of memory devices that are simultaneously accessed, the memory hub further including an N*P-bit input/output port that is operable to receive or transmit M*N data bits in N*P-bit words at a rate of (M*X)/P data words per second, where N and P are respective positive integers; and a communications link coupling the input/output port of the controller to the input/output ports of the memory hubs in the respective memory modules. - View Dependent Claims (54, 55, 56)
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57. A computer system, comprising:
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a central processing unit (“
CPU”
);a system controller coupled to the CPU, the system controller being operable to receive a memory request from the central processing unit and to transmit a corresponding memory request to an input/output port; an input device coupled to the CPU through the system controller; an output device coupled to the CPU through the system controller; a storage device coupled to the CPU through the system controller; a plurality of memory modules, each of the memory modules comprising; a plurality of memory devices arranged in a plurality of M ranks each having an N-bit data bus, the memory devices being operable to read or write data at a rate of X bits per second; a memory hub coupled to the memory devices in each of the ranks, the memory hub being programmable to configure the memory module in a plurality of data formats each corresponding to a respective number of ranks of memory devices that are simultaneously accessed, the memory hub further including an N*P-bit input/output port that is operable to receive or transmit M*N data bits in N*P-bit words at a rate of (M*X)/P data words per second, where N and P are respective positive integers; and a communications link coupling the input/output port of the system controller to the input/output ports of the memory hubs in the respective memory modules. - View Dependent Claims (58, 59)
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60. A computer system, comprising:
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a central processing unit (“
CPU”
);a system controller coupled to the CPU, the system controller being operable to receive a memory request from the central processing unit and to transmit a corresponding memory request to an input/output port; an input device coupled to the CPU through the system controller; an output device coupled to the CPU through the system controller; a storage device coupled to the CPU through the system controller; a plurality of memory modules, each of the memory modules comprising; a plurality of memory devices arranged in a plurality of ranks; and a memory hub operable to receive a memory request at an inputloutput port, the memory hub being coupled to the memory devices in each of the ranks, the memory hub being programmable to configure the memory module in a plurality of data formats each corresponding to a respective number of ranks of memory devices that are simultaneously accessed, the memory hub in a first of the memory modules being programmed to configure the first memory module so that all of the ranks of memory devices in the first memory module are simultaneously addressed, the memory hub in a second of the memory modules being programmed to configure the second memory module so that half of the ranks of memory devices in the second memory module are simultaneously addressed, and the memory hub in a third of the memory modules being programmed to configure the third memory module so that each of the ranks of memory devices in the third memory module are individually addressed; and a communications link coupling the input/output port of the system controller to the input/output ports of the memory hubs in the respective memory modules.
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61. In a computer system, a method of accessing data in a plurality of memory modules each of which contains a plurality of memory devices, the method comprising:
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dividing the memory devices in each of the memory modules into M ranks each of which has an N-bit data bus, the memory devices being operable to read or write data at a rate of X bits per second; configuring each of the memory modules to access the data stored in the memory module in one of a plurality of data formats each corresponding to a respective number of ranks of memory devices that are simultaneously accessed, each of the memory modules being configured to receive or transmit M*N data bits in N*P-bit words at a rate of (M*X)/P data words per second, where N and P are respective positive integers; and accessing data in each of the memory modules in the configured data format.
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Specification