Arbitration system and method for memory responses in a hub-based memory system

• US 7,120,743 B2
• Filed: 10/20/2003
• Issued: 10/10/2006
• Est. Priority Date: 10/20/2003
• Status: Expired due to Fees

• Current Assignee: Round Rock Research LLC
• Original Assignee: Micron Technology, Inc.
• Inventors: Meyer, James W., Kanski, Cory
• Primary Examiner(s): Padmanabhan, Mano
• Assistant Examiner(s): Walter, Craig E
• Application Number:
  US10/690,810
• Publication Number:
  US 20050086441A1
• Time in Patent Office: 1,086 Days
• Field of Search: None
• US Class Current: 711/118
• CPC Class Codes: G06F 13/1605 based on arbitration arbitration in handling access to a common bus or bus system G06F13/36

Abstract

A memory hub includes a local queue that stores local memory responses, a bypass path that passes downstream memory responses, and a buffered queue coupled to the bypass path that stores downstream memory responses from the bypass path. A multiplexer is coupled to the local queue, buffered queue, and the bypass path and outputs responses from a selected one of the queues or the bypass path responsive to a control signal. Arbitration control logic is coupled to the multiplexer and the queues and develops the control signal to control the response output by the multiplexer.

Claims

1. A memory hub, comprising:

a local queue adapted to receive local memory responses, and operable to store the local memory responses;

a bypass path adapted to receive downstream memory responses, and operable to pass the downstream memory responses;

a buffered queue coupled to the bypass path and operable to store downstream memory responses;

a multiplexer coupled to the local queue, buffered queue and bypass path, the multiplexer being operable to output responses from a selected one of the queues or the bypass path responsive to a control signal; and

arbitration control logic coupled to the multiplexer, the arbitration logic operable to develop the control signal to control the selection of responses output by the multiplexer to alternately output a number of memory responses stored in the buffered queue and the same number of memory responses stored in the local queue if the number or a greater number of responses are stored in each queue.

2. The memory hub of claim 1 wherein the arbitration control logic develops the control signal to output memory responses stored in the local queue prior to memory responses stored in the buffered queue.

3. The memory hub of claim 1 wherein the arbitration control logic develops the control signal to output memory responses stored in the buffered queue prior to memory responses stored in the local queue.

4. The memory hub of claim 1 wherein the arbitration control logic assigns a time stamp to each memory request received by the hub.

5. The memory hub of claim 1 wherein each of the local and downstream memory responses comprise data and a header identifying a memory request corresponding to the memory response.

6. A memory hub adapted to receive local memory responses and downstream memory responses, the memory hub operable to store the received memory responses and operable to assign a time stamp to each memory request when the request is received by the memory hub and further operable to apply an arbitration algorithm to provide memory responses from local and buffered queues on an uplink output as a function of the age of a memory request associated with each memory response, the age of each request corresponding to the respective assigned time stamp.

7. The memory hub of claim 6 wherein the memory hub includes the local queue that stores the local memory responses and the buffered queue that stores the downstream memory responses.

8. The memory hub of claim 7 wherein the memory hub further comprises a multiplexer coupled to the local queue, buffered queue, and bypass path, the multiplexer providing responses from one of the queues or bypass path on an output responsive to a control signal.

9. The memory hub of claim 8 wherein the memory hub further comprises arbitration logic coupled to the queues and the multiplexer, and wherein the arbitration logic applies the control signal to the multiplexer to control which memory responses are provided on the output.

10. The memory hub of claim 9 further including a bypass path coupled to the buffered queue and coupled to the multiplexer, the bypass path adapted to receive the downstream memory responses and operable to provide the responses to the multiplexer and the buffered queue.

11. The memory hub of claim 6 wherein each of the local and downstream memory responses comprise data and a header identifying a memory request corresponding to the memory response.

12. A memory module, comprising:

a plurality of memory devices; and

a memory hub coupled to the memory devices, the memory hub including,

a local queue adapted to receive local memory responses, and operable to store the local memory responses;

a bypass path adapted to receive downstream memory responses, and operable to pass the downstream memory responses;

a buffered queue coupled to the bypass path and operable to store downstream memory responses;

a multiplexer coupled to the local queue, buffered queue and bypass path, and operable to output responses from one of the queues or the bypass path responsive to a control signal; and

arbitration control logic coupled to the multiplexer, the arbitration logic operable to develop the control signal to control the selection of responses output by the multiplexer to alternately output a number of memory responses stored in the buffered queue and the same number of memory responses stored in the local queue if the number or a greater number of responses are stored in each queue.

13. The memory module of claim 12 wherein each of the memory devices comprises a synchronous dynamic random access memory.

14. The memory module of claim 13 wherein the arbitration control logic develops the control signal to output memory responses stored in the local queue prior to memory responses stored in the buffered queue.

15. The memory module of claim 13 wherein the arbitration control logic develops the control signal to output memory responses stored in the buffered queue prior to memory responses stored in the local queue.

16. The memory module of claim 12 wherein the arbitration control logic assigns a time stamp to each memory request when the request is received by the hub.

17. The memory module of claim 12 wherein each of the local and downstream memory responses comprise data and a header identifying a memory request corresponding to the memory response.

18. A memory system, comprising:

a memory hub controller;

a plurality of memory modules, each memory module being coupled to adjacent memory modules through respective high-speed links, at least one of the memory modules being coupled to the memory hub controller through a respective high-speed link, and each memory module comprising;

a plurality of memory devices; and

a memory hub coupled to the memory devices, the memory hub comprising,

a local queue adapted to receive local memory responses, and operable to store the local memory responses;

a bypass path adapted to receive downstream memory responses, and operable to pass the downstream memory responses;

a buffered queue coupled to the bypass path and operable to store downstream memory responses;

a multiplexer coupled to the local queue, the buffered queue and the bypass path, and operable to output responses from one of the queues or the bypass path responsive to a control signal; and

arbitration control logic coupled to the multiplexer, the arbitration logic operable to develop the control signal to control the selection of responses output by the multiplexer to alternately output a number of memory responses stored in the buffered queue and the same number of memory responses stored in the local queue if the number or a greater number of responses are stored in each queue.

19. The memory system of claim 18 wherein each of the high-speed links comprises an optical communications link.

20. The memory system of claim 18 wherein at least some of the memory devices comprise synchronous dynamic random access memories.

21. The memory system of claim 18 wherein the arbitration control logic develops the control signal to output memory responses stored in the local queue prior to memory responses stored in the buffered queue.

22. The memory system of claim 18 wherein the arbitration control logic develops the control signal to output memory responses stored in the buffered queue prior to memory responses stored in the local queue.

23. The memory system of claim 18 wherein the arbitration control logic assigns a time stamp to each memory request received by the hub.

24. The memory system of claim 18 wherein each of the local and downstream memory responses comprise data and a header identifying a memory request corresponding to the memory response.

25. A computer system, comprising:

a processor;

a system controller coupled to the processor, the system controller including a memory hub controller;

an input device coupled to the processor through the system controller;

an output device coupled to the processor through the system controller;

a storage device coupled to the processor through the system controller;

a plurality of memory modules, each memory module being coupled to adjacent memory modules through respective high-speed links, at least one of the memory modules being coupled to the memory hub controller through a respective high-speed link, and each memory module comprising;

a plurality of memory devices; and

a memory hub coupled to the memory devices and coupled to the corresponding high-speed links, the memory hub including,

a local queue adapted to receive local memory responses, and operable to store the local memory responses;

a bypass path adapted to receive downstream memory responses, and operable to pass the downstream memory responses;

a buffered queue coupled to the bypass path and operable to store downstream memory responses;

a multiplexer coupled to the local queue, the buffered queue and the bypass path, and operable to output responses from a selected one of the queues or the bypass path responsive to a control signal; and

arbitration control logic coupled to the multiplexer, the arbitration logic operable to develop the control signal to control the selection of responses output by the multiplexer to alternately output a number of memory responses stored in the buffered queue and the same number of memory responses stored in the local queue if the number or a greater number of responses are stored in each queue.

26. The computer system of claim 25 wherein each of the high-speed links comprises an optical communications link.

27. The computer system of claim 25 wherein at least some of the memory devices comprise synchronous dynamic random access memories.

28. The computer system of claim 25 wherein the processor comprises a central processing unit (CPU).

29. The computer system of claim 25 wherein each of the local and downstream memory responses comprise data and a header identifying a memory request corresponding to the memory response.