General purpose register file architecture for aligned simd

• US 7,120,781 B1
• Filed: 06/30/2000
• Issued: 10/10/2006
• Est. Priority Date: 06/30/2000
• Status: Expired due to Term

• Current Assignee: Analog Devices, Inc.
• Original Assignee: Analog Devices, Inc., Intel Corporation
• Inventors: Witt, David B., Aldrich, Bradley C., Kolagotla, Ravi
• Primary Examiner(s): Chan, Eddie
• Assistant Examiner(s): Li, Aimee J.
• Application Number:
  US09/608,983
• Time in Patent Office: 2,293 Days
• Field of Search: 712/223, 712/224, 712/204, 712/201, 711/201
• US Class Current: 712/223
• CPC Class Codes: G06F 9/3001 Arithmetic instructions
• CPC Class Codes: G06F 9/30109 having multiple operands in a single register
• CPC Class Codes: G06F 9/30112 comprising data of variable length
• CPC Class Codes: G06F 9/3824 Operand accessing

Abstract

A register file architecture in a general purpose digital signal processor (DSP) supports alignment independent SIMD (Single Instruction/Multiple Data) operations. The register file architecture includes a register pair and an alignment multiplexer. Two 32 bit grouped words may be loaded into the register pair. Each grouped word includes four 8 bit operands. The alignment state of the 32 bit words may be determined by the two least significant bits (LSBs) of the pointer addresses of the grouped words. These LSBs are used to control the alignment MUX to select n operands from the two 32 bit grouped words and output an aligned 32 bit grouped word to execution units for parallel processing.

Claims

1. An apparatus comprising:

a register pair adapted to store two grouped words comprising in aggregate up to 2n operands, the register pair including a first register and a second register;

a control unit operative to;

prime the apparatus for aligning a plurality of grouped words in a data array by loading first and second grouped words from said plurality of grouped words into the register pair and determining an alignment state of at least one of said first and second grouped words in a first alignment operation; and

load a next one of said plurality of grouped words into one of said first and second registers in each of a plurality of subsequent alignment operations and

an operand selector adapted to select n operands from the two grouped words in said register pair and output an aligned grouped word comprising said n operands in response to a control signal indicative of the alignment state of said two grouped words in each of the first and said subsequent alignment operations,

wherein

the operand selector is connected to one or more execution units such that the aligned group word is output from the operand selector directly to the execution units, and

in each of the subsequent alignment operations, the control unit loads only one grouped word from said plurality of grouped words into the register pair and the operand selector outputs one aligned grouped word from said register pair.

2. The apparatus of claim 1, wherein said operand selector is a multiplexer.

3. The apparatus of claim 1, wherein the control signal comprises the two least significant bits of a pointer address of one of said two grouped words.

4. The apparatus of claim 1, wherein each of the two grouped words and the aligned grouped word comprise 32 bit words.

5. The apparatus of claim 1, wherein n equals 4.

6. The apparatus of claim 1, wherein said n operands comprise 8 bit words.

7. The apparatus of claim 1, wherein said n operands comprise 16 bit words.

8. The apparatus of claim 1, further comprising:

a second register pair adapted to store a second set of two grouped words comprising 2n operands,

wherein said operand selector is adapted to select n operands from said second register pair and output a second aligned grouped word comprising said n operands in response to a control signal indicative of an alignment state of said first set of two grouped words.

9. The apparatus of claim 1, further comprising:

a second register pair adapted to store a second set of two grouped words comprising 2n operands,

wherein said operand selector is adapted to select n operands from said second register pair and output a second aligned grouped word comprising said n operands in response to a control signal indicative of an alignment state of said second set of two grouped words.

10. The apparatus of claim 1, wherein in the subsequent alignment operations, the operand selector selects said n operands and outputs said aligned grouped word without receiving a control signal from the control unit indicating an alignment state of either grouped word in the register pair.

11. The apparatus of claim 1, wherein the operand selector is operative to:

forward multiplex operands in the register pair in the first alignment operation and odd-numbered subsequent alignment operations; and

reverse multiplex operands in the register pair in even-numbered subsequent alignment operations.

12. The apparatus of claim 1, wherein the control unit is operative to disable the generation of exceptions due to misaligned access in the first alignment operation.

13. The apparatus of claim 1, wherein the first alignment operation comprises:

execution of instructions to load the first and second grouped words, and

execution of instructions that generate the aligned grouped word.

14. The apparatus of claim 1, wherein the control signal is generated as part of execution of at least one of an instruction that loads the first grouped word, an instruction that loads the second grouped word, an instruction that loads both the first and second grouped words, or an instruction that generates the aligned group word.

15. A video processor comprising:

a memory to store instructions to perform video processing operations;

a digital signal processor comprising;

a register pair adapted to store two grouped words comprising in aggregate up to 2n operands, the register pair including a first register and a second register;

a control unit operative to;

prime the apparatus for aligning a plurality of grouped words in a data array by loading first and second grouped words from said plurality of grouped words into the register pair and determining an alignment state of at least one of said first and second grouped words in a first alignment operation; and

load a next one of said plurality of grouped words into one of said first and second registers in each of a plurality of subsequent alignment operations; and

an operand selector adapted to select n operands from the two grouped words in said register pair and output an aligned grouped word comprising said n operands in response to a control signal indicative of the alignment state of said two grouped words in each of the first and said subsequent alignment operations,

wherein

the operand selector is connected to one or more execution units such that the aligned group word is output from the operand selector directly to the execution units, and

in each of the subsequent alignment operations, the control unit loads only one grouped word from said plurality of grouped words into the register pair and the operand selector outputs one aligned grouped word from said register pair.

16. The video processor of claim 15, wherein the control signal comprises the two least significant bits of a pointer address of one of first and second grouped words.

17. The video processor of claim 15, wherein each of the first grouped word, second grouped word and the aligned grouped word comprise 32 bit words.

18. The video processor of claim 15, wherein n equals 4.

19. The video processor of claim 15, wherein said n operands comprise 8 bit words.

20. The video processor of claim 15, wherein said n operands comprise 16 bit words.

21. The video processor of claim 15, wherein in the subsequent alignment operations, the operand selector selects said n operands and outputs said aligned grouped word without receiving a control signal from the control unit indicating an alignment state of either grouped word in the register pair.

22. The video processor of claim 15, wherein the operand selector is operative to:

forward multiplex operands in the register pair in the first alignment operation and odd-numbered subsequent alignment operations; and

reverse multiplex operands in the register pair in even-numbered subsequent alignment operations.

23. The video processor of claim 15, wherein the control unit is operative to disable the generation of exceptions due to misaligned access in the first alignment operation.

24. A method comprising:

loading a first grouped word comprising n operands into a register pair;

loading a second grouped word comprising n operands into the register pair;

determining an alignment state of said first and second words;

selecting n operands from the 2n operands in the first and second grouped words in the register pair in response to the determined alignment state, the n operands selected by an operand selector;

outputting from the operand selector directly to one or more execution units an aligned grouped word comprising n operands;

loading a third grouped word comprising n operands;

selecting n operands from the 2n operands in the second and third grouped words in response to the determined alignment state; and

outputting from the operand selector directly to the execution units a second aligned grouped word comprising n operands.

25. The method of claim 24, wherein determining the alignment state comprises determining the two least significant bits of one of said first and second grouped words.

26. The method of claim 24, wherein said first and second grouped words are adjacent words in a data array.

27. The method of claim 26, wherein selecting n operands comprises selecting n adjacent operands in said first and second grouped words.

28. The method of claim 24, wherein selecting n operands comprises reverse multiplexing n operands between the second and third grouped words.

29. The method of claim 24, wherein each of the two grouped words and the aligned grouped word comprise 32 bit words.

30. The method of claim 24, wherein said n operands comprise 8 bit words.

31. An apparatus, including instructions residing on a machine-readable medium, for use aligning operands in a grouped word, the instructions causing the machine to:

load a first grouped word comprising n operands into a register pair;

load a second grouped word comprising n operands into the register pair;

determine an alignment state of said first and second words;

select n operands from the 2n operands in the first and second grouped words in the register pair in response to the determined alignment state, the n operands selected by an operand selector;

output from the operand selector directly to one or more execution units an aligned grouped word comprising n operands;

load a third grouped word comprising n operands;

select n operands from the 2n operands in the second and third grouped words in response to the determined alignment state; and

output from the operand selector directly to the execution units a second aligned grouped word comprising n operands.

32. The apparatus of claim 31, wherein the instructions that cause the machine to determine the alignment state further comprise instructions that cause the machine to determine the two least significant bits of one of said first and second grouped words.

33. The apparatus of claim 31, wherein said first and second grouped words are adjacent words in a data array.

34. The apparatus of claim 33, wherein the instructions that cause the machine to select n operands further comprise instructions that cause the machine to select n adjacent operands in said first and second grouped words.

35. The apparatus of claim 31, wherein the instructions that cause the machine to select n operands further comprise instructions that cause the machine to reverse multiplex n operands between the second and third grouped words.