Apparatus for delay fault testing of integrated circuits

• US 7,120,890 B2
• Filed: 10/28/2003
• Issued: 10/10/2006
• Est. Priority Date: 10/28/2002
• Status: Expired due to Fees

• Current Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Original Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Inventors: Anzou, Kenichi, Tokunaga, Chikako, Hasegawa, Tetsu, Urata, Koji
• Primary Examiner(s): Whitmore, Stacy A
• Application Number:
  US10/695,698
• Publication Number:
  US 20050010886A1
• Time in Patent Office: 1,078 Days
• Field of Search: 716 4- 5, 716/7, 716/12
• US Class Current: 716/108
• CPC Class Codes: G01R 31/31813 Test pattern generators
• CPC Class Codes: G01R 31/31917 Stimuli generation or application of test patterns to the device under test [DUT]
• CPC Class Codes: G01R 31/31919 Storing and outputting test patterns G01R31/31924 takes precedence; arithmetic and random test patterns generator

Abstract

A method for generating a test vector of an IC including: designating a retrieval condition to select a path on which a signal can be transmitted in the circuit; executing a timing analysis of the circuit based on a circuit information of the circuit, retrieving the path satisfying the retrieval condition, and generating a path list in which cells composing the retrieved path are put in order of executing the timing analysis; generating a test vector to test a path delay fault of the circuit based on the path list; designating an ending condition to end generation of the test vector when the path in the path list for the test vector is distributed over the circuit; and stopping generation of the path list when the ending condition is satisfied.

Claims

1. An apparatus for generating a test vector of a semiconductor integrated circuit, comprising:

a retrieval-condition designation section designating a retrieval condition configured to select a path on which a signal can be transmitted in the semiconductor integrated circuit;

a path-list generation section executing a timing analysis of the semiconductor integrated circuit based on circuit information of the semiconductor integrated circuit, retrieving the path satisfying the retrieval condition, and generating a path list in which cells composing the retrieved path are ordered according to the timing analysis;

a test-vector generation section generating a test vector configured to test a path delay fault of the semiconductor integrated circuit based on the path list;

an ending-condition designation section designating an ending condition configured to end generation of the test vector when the path in the path list for the test vector covers the semiconductor integrated circuit; and

an ending-condition judgment section stopping generation of the path list when the ending condition is satisfied.

2. The apparatus as claimed in claim 1, wherein the ending-condition designation section comprises:

a coverage-judging-condition designation section dividing the semiconductor integrated circuit into a plurality of regions and designating a condition configured to judge that the path covers the region; and

a coverage-rate definition section designating a coverage rate as a ratio of the number of the regions which are judged to be covered to the total number of the regions.

3. The apparatus as claimed in claim 2, wherein the retrieval-condition designation section comprises a region designation section displaying a screen image of the semiconductor integrated circuit divided into the regions, requesting designation of the region based on the screen image, and designating the retrieval condition by which the path covering the designated region can be retrieved.

4. The apparatus as claimed in claim 1, wherein the retrieval-condition designation section comprises a circuit-information setting section setting a retrieval item concerning the circuit information and a setting range within which the path is retrieved corresponding to the retrieval item, and the apparatus further comprises one of:

a retrieval-priority decision section deciding priorities among the items to be satisfied by the path to be retrieved; and

a circuit-information changing section relieving the set range in the circuit-information setting section and generating the path list when the ending condition is not satisfied.

5. The apparatus as claimed in claim 1, wherein the retrieval condition includes a circuit-information condition having a retrieval item concerning the circuit information and a set value defining a range within which the path is retrieved corresponding to the retrieval item, and the apparatus further comprises one of:

a retrieval-order condition including priorities among the retrieval items to be satisfied by the path to be retrieved; and

a circuit-information changing condition relieving the set value and generating the path list when the ending condition is not satisfied.

6. The apparatus as claimed in claim 2, further comprising:

a pin-name-list making section making a pin-name list extracting pin names of the cells in the designated regions based on placing and routing of layout information on the cells in the circuit information on the designated regions; and

a circuit-information extraction section extracting the circuit information of the retrieval items by each of the pin-name list.

7. The apparatus as claimed in claim 6, wherein the path-list generation section executes timing analysis and retrieves a path covering the designated regions based on the pin-name list and the circuit information for each of the retrieval items.

8. The apparatus as claimed in claim 6, further comprising:

a path-circuit-information making section making the circuit information for each of the retrieval items of the path covering the designated regions based on the circuit information for each of the extracted retrieval items;

a delimiter-value designation section setting a delimiter value within the setting range and dividing the setting range into a plurality of zones by the delimiter value; and

a distinguished-path displaying section distinguishably displaying the path in each of the zones to which the circuit information for each of the retrieval items of the path belongs and superposing the path on a screen image of the semiconductor integrated circuit.

9. An apparatus for analyzing a failure in a semiconductor integrated circuit, comprising:

a cell-list generation section generating a list of cells composing a path in the semiconductor integrated circuit with a delay fault based on a test result of whether the delay fault is generated on the path;

a retrieval-condition designation section designating a retrieval condition configured to retrieve a fault-cell searching path, which includes a part of the path with the delay fault;

a path-list generation section for fault-cell searching, which retrieves the fault-cell searching path based on the retrieval condition, and generates a fault-cell searching path list in which cells composing the retrieved fault-cell searching path are ordered according to the transmission of a signal by the cells composing the retrieved fault-cell searching path;

a test-vector generation section for fault-cell searching, which generates a test vector based on the fault-cell searching path list;

an ending-condition designation section designating an ending condition configured to end generation of the test vector; and

an ending-condition judgment section stopping generation of the path list when the ending condition is satisfied.

10. The apparatus as claimed in claim 9, wherein the ending condition includes at least one of a condition that a number of generated test vectors exceeds a predetermined number, and a condition that, for each of the generated path lists, at least one attempt has been made to generate a corresponding test vector.

11. The apparatus as claimed in claim 9, wherein a fail path segment along the screen image of the path with the delay fault is displayed in a distinguishable manner from a screen image of the semiconductor integrated circuit including a screen image of the path with the delay fault.

12. The apparatus as claimed in claim 11, wherein a fault-cell searching path segment along the fault-cell searching path is configured to be distinguished from the screen image of the semiconductor integrated circuit, the screen image of the path with the delay fault, and the fail path segment.

13. The apparatus as claimed in claim 9, wherein the retrieval-condition designation section comprises a circuit-information setting section setting a retrieval item concerning the circuit information and a setting range within which the path is retrieved corresponding to the retrieval item, and the apparatus further comprises one of:

a retrieval-priority decision section deciding priorities among the items to be satisfied by the path to be retrieved; and

a circuit-information changing section relieving the set range in the circuit-information setting section and more easily generating the path list when the ending condition is not satisfied.

14. The apparatus as claimed in claim 9, wherein the retrieval condition includes a circuit-information condition having a retrieval item concerning the circuit information and a set value defining a range within which the path is retrieved corresponding to the retrieval item, and the apparatus further comprises one of:

a retrieval-order condition including priorities among the retrieval items to be satisfied by the path to be retrieved; and

a circuit-information changing condition relieving the set value and generating the path list when the ending condition is not satisfied.

15. The apparatus as claimed in claim 9, wherein pin-coordinate information of an input/output pin of the cells composing the path with the delay fault is generated based on a placing and routing of layout information in the circuit information on the semiconductor integrated circuit.

16. The apparatus as claimed in claim 11, wherein the semiconductor integrated circuit is divided into a plurality of regions, and the regions are displayed and distinguished from each other according to the number of the fault paths with the delay fault covering the regions respectively.

17. The apparatus as claimed in claim 9, wherein numbers of the paths with the delay fault are counted for each semiconductor integrated circuit on one wafer, each wafer of one lot, or each lot in a plurality of lots, and the semiconductor integrated circuit, the wafer, or the lot is displayed and distinguished from each other according to the numbers of paths with delay faults.

18. The apparatus as claimed in claim 12, wherein one of the fail path segment and the fault-cell searching path segment is highlighted according to a ratio of one of a measured value of a delay time for the path with the delay fault and a measured value of a delay time measured with the test vector to a calculated value of the delay time respective.

19. A computer-implemented method for generating a test vector of a semiconductor integrated circuit comprising:

designating a retrieval condition configured to select a path on which a signal can be transmitted in the semiconductor integrated circuit;

executing a timing analysis of the semiconductor integrated circuit based on circuit information of the semiconductor integrated circuit, retrieving the path satisfying the retrieval condition, and generating a path list in which cells composing the retrieved path are ordered according to the timing analysis;

generating a test vector configured to test a path delay fault of the semiconductor integrated circuit based on the path list;

designating an ending condition configured to end generation of the test vector when the path in the path list for the test vector covers the semiconductor integrated circuit; and

stopping generation of the path list when the ending condition is satisfied.

20. A computer program product to be executed by a computer for generating a test vector of a semiconductor integrated circuit comprising:

instructions designating a retrieval condition configured to select a path on which a signal can be transmitted in the semiconductor integrated circuit;

instructions executing a timing analysis of the semiconductor integrated circuit based on circuit information of the semiconductor integrated circuit, retrieving the path satisfying the retrieval condition, and generating a path list in which cells composing the retrieved path are ordered according to the timing analysis;

instructions generating a test vector configured to test a path delay fault of the semiconductor integrated circuit based on the path list;

instructions designating an ending condition configured to end generation of the test vector when the path in the path list for the test vector covers the semiconductor integrated circuit; and

instructions stopping generation of the path list when the ending condition is satisfied.