System and method for lithography simulation

• US 7,120,895 B2
• Filed: 03/18/2005
• Issued: 10/10/2006
• Est. Priority Date: 10/07/2003
• Status: Active Grant

• Current Assignee: ASML Netherlands BV (ASML Holding NV)
• Original Assignee: Brion Technologies Incorporated (ASML Holding NV)
• Inventors: Ye, Jun, Chen, Luoqi, Chen, Xun, Lu, Yen-Wen, Cao, Yu
• Primary Examiner(s): Kik, Phallaka
• Application Number:
  US11/084,484
• Publication Number:
  US 20050166174A1
• Time in Patent Office: 571 Days
• Field of Search: 716/21, 430/5, 378/35, 700/97, 700/120, 700/121, 250/492.22
• US Class Current: 716/51
• CPC Class Codes: G03F 1/00 Originals for photomechanical production of textured or patterned surfaces, e.g., masks, photo-masks, reticles; Mask blanks or pellicles therefor; Containers specially adapted therefor; Preparation thereof
• CPC Class Codes: G03F 7/004 Photosensitive materials G03F7/12, G03F7/14 take precedence
• CPC Class Codes: G03F 7/705 Modelling or simulating from physical phenomena up to complete wafer processes or whole workflow in wafer productions
• CPC Class Codes: G03F 7/70666 Aerial image, i.e. measuring the image of the patterned exposure light at the image plane of the projection system
• CPC Class Codes: G06F 2119/18 Manufacturability analysis or optimisation for manufacturability
• CPC Class Codes: G06F 30/20 Design optimisation, verification or simulation optimisation, verification or simulation of circuit designs G06F30/30
• CPC Class Codes: G06F 30/333 Design for testability [DFT], e.g. scan chain or built-in self-test [BIST]
• CPC Class Codes: G06F 30/398 Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM] optical proximity correction [OPC] design processes G03F1/36
• CPC Class Codes: G06T 2207/30148 Semiconductor; IC; Wafer
• CPC Class Codes: G06T 7/0004 Industrial image inspection
• CPC Class Codes: G16Z 99/00 Subject matter not provided for in other main groups of this subclass
• CPC Class Codes: G21K 5/00 Irradiation devices discharge tubes for irradiating H01J37/00

Abstract

There are many inventions described and illustrated herein. In one aspect, the present invention is directed to a technique of, and system for simulating, verifying, inspecting, characterizing, determining and/or evaluating the lithographic designs, techniques and/or systems, and/or individual functions performed thereby or components used therein. In one embodiment, the present invention is a system and method that accelerates lithography simulation, inspection, characterization and/or evaluation of the optical characteristics and/or properties, as well as the effects and/or interactions of lithographic systems and processing techniques. In this regard, in one embodiment, the present invention employs a lithography simulation system architecture, including application-specific hardware accelerators, and a processing technique to accelerate and facilitate verification, characterization and/or inspection of a mask design, for example, RET design, including detailed simulation and characterization of the entire lithography process to verify that the design achieves and/or provides the desired results on final wafer pattern. The system includes: (1) general purpose-type computing device(s) to perform the case-based logic having branches and inter-dependency in the data handling and (2) accelerator subsystems to perform a majority of the computation intensive tasks.

Claims

1. A method to evaluate a design pattern on a photolithographic mask to a change in at least one process parameter of a photolithographic process, wherein the photolithographic process uses photolithographic equipment, the method comprising:

generating a first simulated image of a lithographic design on a wafer using (1) a pixel-based bitmap of the design pattern on the photolithographic mask and (2) a first relationship representing an imaging path of the projection and illumination optics of the photolithographic process, wherein the pixel-based bitmap of the design pattern on the photolithographic mask is generated using an image of the photolithographic mask; and

generating a second simulated image of the lithographic design on a wafer using (1) the pixel-based bitmap of the design pattern on the photolithographic mask and (2) a second relationship representing the imaging path of the projection and illumination optics of the photolithographic process, wherein a difference between (i) the first relationship representing the imaging path of the projection and illumination optics of the photolithographic process and (ii) the second relationship representing the imaging path of the projection and illumination optics of the photolithographic process includes the change in the at least one process parameter of the photolithographic process; and

evaluating the design pattern on a photolithographic mask to the change in at least one process parameter of a photolithographic process by;

comparing the first simulated image of the lithographic design on a wafer and a design target on the wafer which corresponds to the design pattern on the photolithographic mask; and

comparing the second simulated image of the lithographic design on a wafer and the design target on the wafer.

2. The method of claim 1, further including determining whether a response of the design pattern on the photolithographic mask to the change in at least one process parameter of the photolithographic process exceeds a process window using (1) the comparison of the first simulated image of the lithographic design on wafer and the design target on the wafer, and (2) the comparison of the second simulated image of the lithographic design on a wafer and the design target on the wafer.

3. The method of claim 1, further including determining a response of the design pattern on the photolithographic mask to the change in at least one process parameter of the photolithographic process using the first and second simulated images of the lithographic design.

4. The method of claim 3, wherein determining the response of the design pattern on the photolithographic mask to the change in the at least one process parameter of the photolithographic process further includes determining a critical dimension sensitivity of the design pattern on the photolithographic mask to the change in the at least one process parameter of the photolithographic process.

5. The method of claim 4, wherein determining the critical dimension sensitivity of the design pattern on the photolithographic mask to the change in the at least one process parameter of the photolithographic process further includes determining a plurality of derivatives as the critical dimension sensitivity of the design pattern on the photolithographic mask.

6. The method of claim 3, further including determining lithography settings using the determined response of the design pattern on the photolithographic mask to the change in the at least one process parameter of the photolithographic process.

7. The method of claim 6, wherein the lithographic settings include at least one of photolithographic settings of the photolithographic equipment, resist processing parameters or resist stack design.

8. The method of claim 1, wherein the change in the at least one process parameter of the photolithographic process is a change in focus, illumination dose, numerical aperture or illumination aperture of the photolithographic equipment.

9. The method of claim 8, wherein the design pattern on the photolithographic mask is a localized region of an integrated circuit design on the photolithographic mask.

10. The method of claim 1, further including determining a configuration of settings of the photolithographic equipment using (1) the comparison of the first simulated image of the lithographic design on wafer and the design target on the wafer and (2) the comparison of the second simulated image of the lithographic design on wafer and the design target on the wafer.

11. The method of claim 10, wherein the configuration of settings of the photolithographic equipment includes at least one of focus, illumination dose, numerical aperture or illumination aperture of the photolithographic equipment.

12. The method of claim 1, wherein the first and second relationships representing the imaging path of the projection and illumination optics are coefficient matrices representing the imaging path of the projection and illumination optics of the photolithographic equipment.

13. The method of claim 12, wherein the coefficient matrices are representative of one or more of a focus, dose, numerical aperture, illumination aperture, and aberration of the photolithographic equipment.

14. A system to evaluate a design pattern on a photolithographic mask to a change in at least one process parameter of a photolithographic process, wherein the photolithographic process uses photolithographic equipment, the system comprising:

a plurality of accelerator subsystems, each accelerator subsystem includes a plurality of programmable integrated circuits configured to process, in parallel, a pixel-based bitmap of the design pattern on the photolithographic mask, wherein the pixel-based bitmap of the design pattern on the photolithographic mask is generated using an image of the photolithographic mask, and wherein each accelerator subsystem is connected to an associated microprocessor to calculate;

a portion of a first of simulated image of lithographic design on wafer using (1) a corresponding portion of the pixel-based bitmap of the design pattern on the photolithographic mask and (2) a first relationship representing an imaging path of the projection and illumination optics of the photolithographic process,

a portion of a second of simulated image of the lithographic design on wafer using (1) a corresponding portion of the pixel-based bitmap of the design pattern on the photolithographic mask and (2) a second relationship representing the imaging path of the projection and illumination optics of the photolithographic process, wherein a difference between the first and second relationships representing the imaging path of the projection and illumination optics of the photolithographic process includes a change in the at least one process parameter of the photolithographic process; and

a data processing system, coupled to the plurality of accelerator subsystems, to determine whether the design pattern on the photolithographic mask includes one or more defects by;

comparing (i) the first simulated image of the lithographic design on wafer and (ii) a design target on the wafer which corresponds to the design pattern on the photolithographic mask; and

comparing (i) the second simulated image of the lithographic design on wafer and (ii) the design target on the wafer.

15. The system of claim 14, wherein the change in the at least one process parameter of the photolithographic process is a change in focus, illumination dose, numerical aperture or illumination aperture of the photolithographic equipment.

16. The system of claim 14, wherein the data processing system further determines whether a response of the design pattern on the photolithographic mask to the change in at least one process parameter of the photolithographic process exceeds a process window using (1) the comparison of the first simulated image of the lithographic design on wafer and the design target on the wafer, and (2) the comparison of the second simulated image of the lithographic design on a wafer and the design target on the wafer.

17. The system of claim 14, wherein the relationships representing the imaging path of the projection and illumination optics includes a coefficient matrix representing the imaging path of the projection and illumination optics of the photolithographic equipment.

18. The system of claim 17, wherein the coefficient matrix representing the imaging path of the projection and illumination optics of the photolithographic equipment is representative of one or more of a focus, dose, numerical aperture, illumination aperture, and aberration of the photolithographic equipment.

19. The system of claim 14, wherein design pattem on the photolithographic mask is a localized region of an integrated circuit design on the photolithographic mask.

20. The system of claim 14, wherein the data processing system further determines a response of the design pattern on the photolithographic mask to the change in at least one process parameter of the photolithographic process using the first and second simulated images of the lithographic design on wafer.

21. The system of claim 20, wherein the data processing system further calculates settings of the photolithographic equipment using the determination of the response of the design pattern on the photolithographic mask to the change in at least one process parameter of the photolithographic process.

22. The system of claim 21, wherein the settings of the photolithographic equipment include at least one of the focus, illumination dose, numerical aperture or illumination aperture of the photolithographic equipment.

23. The system of claim 14, wherein the data processing system further determines a critical dimension sensitivity of the design pattern on the photolithographic mask to the change in the at least one process parameter of the photolithographic process using the first and second simulated images.

24. The system of claim 23, wherein the critical dimension sensitivity of the design pattern on the photolithographic mask to the change in the at least one process parameter of the photolithographic process includes a plurality of derivatives as the critical dimension sensitivity of the design pattern on the photolithographic mask to the change in at least one process parameter of the photolithographic process.

25. The system of claim 14, wherein the data processing system further determines a set of parameters of the projection and illumination optics of the photolithographic process using the first and second simulated images of the lithographic design on wafer.

26. The system of claim 14, wherein the data processing system further detects whether the design pattern on the photolithographic mask exceeds a process window using the first and second simulated images of the lithographic design on wafer.

27. The system of claim 26, wherein, in response to detecting the design pattern on the photolithographic mask that exceeds the process window, the data processing system further determines a modification to the design pattern.

28. The system of claim 26, wherein, in response to detecting the design pattern on the photolithographic mask that exceeds the process window, the data processing system further determines a change to at least one parameter of the photolithographic process.