Processor power-saving control method, storage medium, and processor power-saving control device

• US 7,120,911 B1
• Filed: 11/20/2000
• Issued: 10/10/2006
• Est. Priority Date: 03/08/2000
• Status: Expired due to Fees

• Current Assignee: Mitsubishi Denki Kabushiki Kaisha (Mitsubishi Electric Corporation)
• Original Assignee: Mitsubishi Denki Kabushiki Kaisha (Mitsubishi Electric Corporation)
• Inventors: Katayama, Yoshiaki
• Primary Examiner(s): BULLOCK JR, LEWIS ALEXANDER
• Application Number:
  US09/926,468
• Time in Patent Office: 2,150 Days
• Field of Search: 718100-108, 713300-323, 713/330, 710/260
• US Class Current: 718/102
• CPC Class Codes: G06F 1/3228 Monitoring task completion, e.g. by use of idle timers, stop commands or wait commands

Abstract

The present invention is employed in the environment in which a plurality of OSs exist on a single processor having a power-saving function, and includes a primary OS for receiving a timer interrupt from a hardware timer after a predetermined time lapse and a secondary OS treated as a task to be executed by the primary OS, wherein upon receiving the timer interrupt, the primary OS determines whether there exists any task to be executed, and interrupts the secondary OS if there is any task to be executed on the secondary OS.

Claims

1. A processor power-saving control method which employs a plurality of Operating Systems (OSs) whose execution is controlled by a processor, wherein said plurality of OSs include

a primary OS for receiving a timer interrupt issued from a hardware timer after a predetermined time lapse, and

a secondary OS treated as a task to be executed by said primary OS, said processor power-saving control method comprising the steps of:

receiving said timer interrupt at said primary OS;

determining with said primary OS whether there exists any task scheduled to be executed on said secondary OS;

interrupting said secondary OS by issuing a secondary-OS interrupt from the primary OS to the secondary OS when the primary OS determines there exists any task scheduled to be executed on said secondary OS; and

removing the secondary OS from a power-saving mode in response to the secondary OS receiving the secondary OS-interrupt issued from the primary OS.

2. The method of claim 1, wherein removing the secondary OS from the power-saving mode further comprises increasing a frequency of a processor clock signal.

3. The method of claim 1, wherein removing the secondary OS from the power-saving mode further comprises exiting a sleep mode using a sleep Application Program Interface (API).

4. A processor power-saving control method which employs a plurality of Operating Systems (OSs) whose execution is controlled by a processor,

operation of said processor being placed in a power-saving mode when there exists no task scheduled to be executed on said plurality of OSs,

said processor power-saving control method controlling timer interrupt processing performed by a hardware timer which causes said processor to exit the power-saving mode after an arbitrary time lapse,

said processor power-saving control method keeping a power-saving state of said processor,

said plurality of OSs including a primary OS for receiving a timer interrupt issued from said hardware timer and a secondary OS treated as a task to be executed by said primary OS,

said processor power-saving control method comprising:

a primary-OS process step performed by said primary OS;

a secondary-OS process step performed by said secondary OS; and

a secondary-OS interrupt step,

said primary-OS process step including

detecting said timer interrupt,

a first determination step of, upon receiving said timer interrupt, determining whether there exists any task scheduled to be executed, and

a processor stopping step of placing said processor in the power-saving mode when there is no task scheduled to be executed;

said secondary-OS process step including

a second determination step of determining whether there exists any task scheduled to be executed, and

handing over processing to said first determination step when there is no task scheduled to be executed;

said secondary-OS interrupt step including

receiving a secondary-OS interrupt from said primary OS,

performing interrupt processing on said secondary OS when said first determination step has determined that there exists any task scheduled to be executed on said secondary OS, and

executing said second determination step at a predetermined time measured from said interrupt.

5. The processor power-saving control method as claimed in claim 4, wherein said secondary-OS interrupt step is executed by a periodically-activating handler which interrupts said secondary OS at regular time intervals.

6. The processor power-saving control method as claimed in claim 4, wherein said secondary-OS interrupt step is executed by an alarm handler which interrupts said secondary OS after a specified time period.

7. The processor power-saving control method as claimed in claim 4, wherein said secondary-OS interrupt step is executed by a high-priority task which is a task for interrupting said secondary OS and has a highest priority order among tasks scheduled to be executed by said primary OS.

8. The processor power-saving control method as claimed in claim 4, wherein said processor stopping step includes a step of determining whether time taken until said hardware timer issues a next timer interrupt is longer than a predetermined time, and if a measured time is longer than said predetermined time, said processor stopping step stops operation of said processor.

9. The processor power-saving control method as claimed in claim 4, wherein said primary-OS process step further comprises steps of:

when said hardware timer periodically performs timer interrupt processing at regular time intervals, determining whether timer interrupt processing is required again by a time at which a task is scheduled to be executed; and

if timer interrupt processing is not required again, stopping said hardware timer.

10. The processor power-saving control method as claimed in claim 9, wherein said primary-OS process step further comprises a step of:

detecting a timer interrupt issued by a long-periodic hardware timer which issues a timer interrupt at a time interval longer than that of said hardware timer.

11. The processor power-saving control method as claimed in claim 4, wherein said primary-OS process step further comprises a step of:

detecting a timer interrupt issued by a time-of-day timer which measures a time of day as well as issuing a timer interrupt at a predetermined time of day.

12. The process power-saving control method of claim 4, wherein the secondary-OS interrupt step further includes the step of:

activating the secondary OS from the power-saving mode in response to the secondary OS receiving the secondary-OS interrupt from the primary OS.

13. The method of claim 12, wherein activating the secondary OS from the power saving mode further comprises increasing a frequency of a processor clock signal.

14. The method of claim 12, wherein activating the secondary OS from the power saving mode further exiting a sleep mode using a sleep Application Program Interface (API).

15. The method of claim 4, wherein placing said processor in the power-saving mode further comprises reducing a frequency of a processor clock signal.

16. The method of claim 4, wherein placing said processor in the power-saving mode further comprises stopping a processor clock signal.

17. The method of claim 4, wherein placing said processor in the power-saving mode further comprises entering a sleep mode using a sleep Application Program Interface (API).

18. A computer readable storage medium storing a plurality of Operating Systems (OSs) whose execution is controlled by a processor which is stopped when there exists no task scheduled to be executed, said plurality of OSs including a primary OS for receiving a timer interrupt issued from a hardware timer which activates said processor after an arbitrary time lapse, and a secondary OS treated as a task to be executed by said primary OS,

wherein said computer readable storage medium stores a program which causes a computer to perform:

a primary-OS process step on said primary OS;

a secondary-OS process step on said secondary OS; and

a secondary-OS interrupt step,

said primary-OS process step including

detecting said timer interrupt issued by said hardware timer,

a first determination step of, upon detecting said timer interrupt, determining whether there exists any task scheduled to be executed, and

a processor stopping step of placing said processor in a power-saving mode where there is no task scheduled to be executed;

said secondary-OS process step including

a second determination step of determining whether there exists any task scheduled to be executed, and

handing over processing to said first determination step when there is no task scheduled to be executed;

said secondary-OS interrupt step including

receiving a secondary-OS interrupt from said primary OS,

performing interrupt processing on said secondary OS when said first determination step has determined that there exists any task scheduled to be executed on said secondary OS, and

executing said second determination step at a predetermined time measured from said interrupt.

19. The computer readable storage medium of claim 18, wherein the secondary-OS interrupt step includes the step of:

activating the secondary OS from the power-saving mode in response to the secondary OS receiving the secondary-OS interrupt from the primary OS.

20. The method of claim 19, wherein activating the secondary OS from the power saving mode further comprises increasing a frequency of a processor clock signal.

21. The method of claim 19, wherein activating the secondary OS from the power saving mode further exiting a sleep mode using a sleep Application Program Interface (API).

22. The computer readable storage medium of claim 18, wherein placing said processor in the power-saving mode further comprises reducing a frequency of a processor clock signal.

23. The computer readable storage medium of claim 18, wherein placing said processor in the power-saving mode further comprises stopping a processor clock signal.

24. The computer readable storage medium of claim 18, wherein placing said processor in the power-saving mode further comprises entering a sleep mode using a sleep Application Program Interface (API).

25. A processor power-saving control device comprising:

a timer device including a hardware timer configured to issue a timer interrupt after an arbitrary time lapse, and activate a processor, operation of said processor being placed in a power-saving mode when there exists no task scheduled to be executed; and

a storage device configured to store a primary Operating System (OS) and a secondary OS;

wherein said primary OS, upon receiving said timer interrupt at said primary OS, is configured to determine whether there exists any task scheduled to be executed, and to cause said processor to enter the power-saving mode if there is no task scheduled to be executed and to issue a secondary-OS interrupt if there is any task scheduled to be executed; and

said secondary OS, upon receiving the secondary-OS interrupt from said primary OS, is configured to determine whether there exists any task scheduled to be executed, and if there is any task scheduled to be executed, to execute the task, said secondary OS being treated as a task scheduled to be executed by said primary OS.

26. The processor power-saving control device as claimed in claim 25, wherein said timer device has a long-periodic timer which issues a timer interrupt at a time interval longer than that of said hardware timer.

27. The processor power-saving control device as claimed in claim 25, wherein said timer device has a time-of-day timer.

28. The processor power-saving control device as claimed in claim 25, wherein said secondary OS is further configured to activate from the power-saving mode in response to the receipt of the secondary-OS interrupt.

29. The device of claim 28, wherein the secondary OS is further configured to activate from the power-saving mode by increasing a frequency of a processor clock signal.

30. The device of claim 28, wherein the secondary OS is further configured to activate from the power-saving mode by exiting a sleep mode using a sleep Application Program Interface (API).

31. The device of claim 25, wherein the primary OS is further configured to cause the processor to enter the power-saving mode by reducing a frequency of a processor clock signal.

32. The device of claim 25, wherein the primary OS is further configured to cause the processor to enter the power-saving mode by stopping a processor clock signal.

33. The device of claim 25, wherein the primary OS is further configured to cause the processor to enter the power-saving mode by entering a sleep mode using a sleep Application Program Interface (API).