SOI device with reduced drain induced barrier lowering
First Claim
1. A method for fabricating an integrated circuit, comprising:
- providing a substrate having a semiconductor layer overlying an insulating layer;
doping the insulating layer with electrical dopant; and
diffusing electrical dopant from the insulating layer out into the semiconductor layer by exposing the substrate to an elevated temperature, wherein a concentration of electrical dopant in the seminconductor layer defines a retrograde dopant profile after diffusing.
5 Assignments
0 Petitions
Accused Products
Abstract
A CMOS device formed with a Silicon On Insulator (SOI) technology with reduced Drain Induced Barrier Lowering (DIBL) characteristics and a method for producing the same. The method involves a high energy, high dose implant of boron and phosphorus through the p- and n-wells, into the insulator layer, thereby creating a borophosphosilicate glass (BPSG) structure within the insulation layer underlying the p- and n-wells of the SOI wafer. Backend high temperature processing steps induce diffusion of the boron and phosphorus contained in the BPSG into the p- and n-wells, thereby forming a retrograde dopant profile in the wells. The retrograde dopant profile reduces DIBL and also provides recombination centers adjacent the insulator layer and the active layer to thereby reduce floating body effects for the CMOS device.
-
Citations
39 Claims
-
1. A method for fabricating an integrated circuit, comprising:
-
providing a substrate having a semiconductor layer overlying an insulating layer; doping the insulating layer with electrical dopant; and diffusing electrical dopant from the insulating layer out into the semiconductor layer by exposing the substrate to an elevated temperature, wherein a concentration of electrical dopant in the seminconductor layer defines a retrograde dopant profile after diffusing. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20)
-
-
21. A method for forming an integrated circuit, comprising:
-
providing a silicon region disposed above an insulator; forming dopant diffusion sources in the insulator, wherein the dopant diffusion sources comprise electrical dopants; forming electrical devices over the dopant diffusion sources; and subsequently establishing a retrograde doping profile in desired parts of the silicon region by diffusion of the electrical dopants out of the diffusion sources and into the silicon region, wherein diffusion is caused by forming electrical devices. - View Dependent Claims (22, 23, 24, 25, 26, 27, 28, 29, 30, 31)
-
-
32. A method for integrated circuit fabrication, comprising:
- providing a substrate having an electrical device overlying a semiconductor layer, the semiconductor layer overlying an insulating layer;
providing a region comprising electrical dopants in the insulating layer; and processing the substrate at an elevated temperature to cause diffusion of electrical dopants out of the insulating layer and into the semiconductor layer, wherein diffusion establishes a retrograde electrical dopant profile in the semiconductor layer. - View Dependent Claims (33, 34, 35, 36, 37, 38, 39)
- providing a substrate having an electrical device overlying a semiconductor layer, the semiconductor layer overlying an insulating layer;
Specification