Bonding pad for gallium nitride-based light-emitting devices

• US 7,122,841 B2
• Filed: 06/03/2004
• Issued: 10/17/2006
• Est. Priority Date: 06/04/2003
• Status: Expired due to Fees

• Current Assignee: Kopin Corporation
• Original Assignee: Kopin Corporation
• Inventors: Oh, Tchang-Hun, Choi, Hong K., Fan, John C. C., Narayan, Jagdish
• Primary Examiner(s): LOUIE, WAI SING
• Application Number:
  US10/860,798
• Publication Number:
  US 20040262621A1
• Time in Patent Office: 866 Days
• Field of Search: None
• US Class Current: 257/81
• CPC Class Codes: H01L 21/28575 on semiconductor bodies comprising AIIIBV compounds
• CPC Class Codes: H01L 29/2003 Nitride compounds
• CPC Class Codes: H01L 29/452 on AIII-BV compounds
• CPC Class Codes: H01L 33/32 containing nitrogen
• CPC Class Codes: H01L 33/40 Materials therefor

Abstract

A semiconductor device includes a substrate having a first major surface; a semiconductor device structure over the first surface of the substrate, the device structure comprising an n-type semiconductor layer, and a p-type semiconductor layer over the n-type semiconductor layer; a p-side electrode having a first and a second surface, wherein the first surface is in electrical contact with the p-type semiconductor layer; and a p-side bonding pad over the p-side electrode. Preferably, the semiconductor device further comprises an n-side bonding pad over an n-type semiconductor layer. The p-side and n-side bonding pads each independently includes a gold layer as its top layer and a single or multiple layers of a diffusion barrier under the top gold layer. Optionally, one or more metal layers are further included under the diffusion barrier. Typically, the p-side bonding pad is formed on the p-side electrode. The n-side bonding pad typically is formed on the n-type semiconductor layer, and forms a good ohmic contact with the n-type semiconductor layer.

Claims

1. A semiconductor device, comprising:

a) a substrate having a first major surface;

b) a semiconductor device structure over the first major surface of the substrate, the device structure comprising a nitride-based n-type semiconductor layer, and a nitride-based p-type semiconductor layer over the n-type semiconductor layer;

c) a p-side electrode having a first and a second surface, wherein the first surface is in electrical contact with the p-type semiconductor layer; and

d) a p-side bonding pad that is in contact with the second surface of the p-side electrode, and that includes;

i) a top gold layer having a first and a second surface, wherein the first surface is the top surface of the p-side bonding pad; and

ii) a single or multiple layers of a p-side diffusion barrier in contact with the second surface of the top gold layer, wherein the p-side diffusion barrier is a single or multiple layers of tungsten, tantalum, molybdenum, chromium, titanium or a mixture thereof,

wherein the p-side bonding pad further comprises one or more metal layers under the p-side diffusion barrier, at least one of said metal layers being in contact with the second surface of the p-side electrode and wherein each of the metal layers under the p-side diffusion barrier is independently selected from the group consisting of gold, palladium, aluminum and a mixture thereof.

2. The device of claim 1, wherein the p-side diffusion barrier is a tantalum layer.

3. The device of claim 2, further including a second gold layer under the tantalum layer.

4. The device of claim 3, further including an aluminum layer under the second gold layer.

5. The device of claim 4, further including a palladium layer under the aluminum layer.

6. A semiconductor device, comprising:

a) a substrate having a first major surface;

b) a semiconductor device structure over the first major surface of the substrate, the device structure comprising a nitride-based n-type semiconductor layer, and a nitride-based p-type semiconductor layer over the n-type semiconductor layer;

c) a p-side electrode having a first and a second surface, wherein the first surface is in electrical contact with the p-type semiconductor layer;

d) a p-side bonding pad that is in contact with the second surface of the p-side electrode, and that includes;

i) a top gold layer having a first and a second surface, wherein the first surface is the top surface of the p-side bonding pad; and

ii) a single or multiple layers of a p-side diffusion barrier in contact with the second surface of the top gold layer, wherein the p-side diffusion barrier is a single or multiple layers of tungsten, tantalum, molybdenum, chromium, titanium or a mixture thereof; and

e) an n-side bonding pad that is directly on a surface of the n-type semiconductor layer and forms an ohmic contact with the underlying n-type semiconductor, wherein the n-side bonding pad includes;

i) a top gold layer having a first and a second surface, wherein the first surface is the top surface of the n-side bonding pad; and

ii) a single or multiple layers of an n-side diffusion barrier in contact with the second surface of the top gold layer.

7. The device of claim 6, wherein the n-side diffusion barrier is a single or multiple layers of tungsten, tantalum, molybdenum, chromium, titanium or a mixture thereof.

8. The device of claim 7, wherein the n-side diffusion barrier includes multiple layers, and wherein said multiple layers of the n-side diffusion barrier are separated by a single or multiple layers of gold.

9. The device of claim 7, wherein the n-side diffusion barrier is a tantalum layer.

10. The device of claim 9, wherein the thickness of the n-side diffusion barrier is in a range of between about 10 Å

to about 3000 Å

.

11. The device of claim 10, wherein the thickness of the n-side diffusion barriers is in a range of between about 50 Å

to about 500 Å

.

12. The device of claim 7, wherein the n-side bonding pad further comprises one or more metal layers under the n-side diffusion barrier, at least one of said metal layers being in contact with a surface of the n-type semiconductor layer.

13. The device of claim 12, wherein each of the metal layers under the n-side diffusion barrier is independently selected from the group consisting of gold, palladium, aluminum and a mixture thereof.

14. The device of claim 13, wherein the n-side diffusion barrier is a tantalum layer.

15. The device of claim 14, further including a second gold layer under the tantalum layer.

16. The device of claim 15, further including an aluminum layer under the second gold layer.

17. The device of claim 16, further including a palladium layer under the aluminum layer.

18. A semiconductor device, comprising:

a) a substrate having a first major surface;

b) a semiconductor device structure over the first major surface of the substrate, the device structure comprising an n-type gallium nitride-based semiconductor layer, and a p-type gallium nitride-based semiconductor layer over the n-type semiconductor layer;

c) a p-side electrode having a first and a second surface, wherein the first surface of the p-side electrode is in electrical contact with the p-type semiconductor layer; and

d) a p-side bonding pad that is in contact with the second surface of the p-side electrode, comprising;

i) a top gold layer having a first and a second surface, wherein the first surface is the top surface of the p-side bonding pad;

ii) a single or multiple layers of a p-side diffusion barrier in contact with the second surface of the top gold layer, wherein the p-side diffusion barrier includes at least one element selected from the group consisting of tungsten, tantalum, molybdenum, and chromium; and

iii) optionally one or more metal layers under the p-side diffusion barrier, wherein each of the metal layers independently is selected from the group consisting of gold, palladium, aluminum and a mixture thereof.

19. The device of claim 18, wherein the p-side diffusion barrier includes multiple layers, and wherein said multiple layers of the p-side diffusion barrier are separated by a single or multiple layers of gold.

20. The device of claim 18, further comprising an n-side bonding pad that is directly on a surface of the n-type semiconductor layer and forms an ohmic contact with the underlying n-type semiconductor, wherein the n-side bonding pad includes:

i) a top gold layer having a first and a second surface, wherein the first surface is the top surface of the n-side bonding pad; and

ii) a single or multiple layers of an n-side diffusion barrier in contact with the second surface of the top gold layer of the n-side bonding pad, wherein the n-side diffusion barrier includes at least one element selected from the group consisting of tungsten, tantalum, molybdenum, chromium and titanium; and

iii) optionally one or more metal layers under the n-side diffusion barrier, each of the metal layers independently selected from the group consisting of gold, palladium, aluminum and a mixture thereof.

21. The device of claim 20, wherein the n-side diffusion barrier includes multiple layers, and wherein said multiple layers of the n-side diffusion barrier are separated by a single or multiple layers of gold.

22. The device of claim 20, wherein each of the diffusion barriers of the n-side and p-side bonding pads is a tantalum layer.

23. The device of claim 22, wherein the n-side bonding pad and/or p-side bonding pad each independently further includes:

a second gold layer under the tantalum layer;

an aluminum layer under the second gold layer; and

a palladium layer under the aluminum layer.

24. A semiconductor device, comprising:

a) a substrate having a first major surface;

b) a semiconductor device structure over the first major surface of the substrate, the device structure comprising an n-type semiconductor layer, and a p-type semiconductor layer over the n-type semiconductor layer;

c) a p-side electrode having a first and a second surface, wherein the first surface is in electrical contact with the p-type semiconductor layer; and

d) a p-side bonding pad that is in contact with the second surface of the p-side electrode, and that includes;

i) a top gold layer having a first and a second surface, wherein the first surface is the top surface of the p-side bonding pad; and

ii) a single or multiple layers of a p-side diffusion barrier in contact with the second surface of the top gold layer, wherein the p-side diffusion barrier is a single or multiple layers of tungsten, tantalum, molybdenum, chromium, titanium or a mixture thereof,

wherein the p-side bonding pad further comprises one or more metal layers under the p-side diffusion barrier, at least one of said metal layers being in contact with the second surface of the p-side electrode and wherein each of the metal layers under the p-side diffusion barrier is independently selected from the group consisting of gold, palladium, aluminum and a mixture thereof.

25. A semiconductor device, comprising:

a) a substrate having a first major surface;

b) a semiconductor device structure over the first major surface of the substrate, the device structure comprising an n-type semiconductor layer, and a p-type semiconductor layer over the n-type semiconductor layer;

c) a p-side electrode having a first and a second surface, wherein the first surface is in electrical contact with the p-type semiconductor layer; and

d) an n-side bonding pad that is directly on a surface of the n-type semiconductor layer and forms an ohmic contact with the underlying n-type semiconductor, wherein the n-side bonding pad includes;

i) a top gold layer having a first and a second surface, wherein the first surface is the top surface of the n-side bonding pad; and

ii) a single or multiple layers of an n-side diffusion barrier in contact with the second surface of the top gold layer, wherein the n-side diffusion barrier is a single or multiple layers of tungsten, tantalum, molybdenum, chromium, titanium or a mixture thereof.