Stressed semiconductor device structures having granular semiconductor material

• US 7,122,849 B2
• Filed: 11/14/2003
• Issued: 10/17/2006
• Est. Priority Date: 11/14/2003
• Status: Expired due to Fees

• Current Assignee: GlobalFoundries, Inc.
• Original Assignee: International Business Machines Corporation
• Inventors: Chidambarrao, Dureseti, Gluschenkov, Oleg, Doris, Bruce B, Belyansky, Michael P, Boyd, Diane C
• Primary Examiner(s): LINDSAY JR, WALTER LEE
• Application Number:
  US10/707,018
• Publication Number:
  US 20050106799A1
• Time in Patent Office: 1,068 Days
• Field of Search: 257/288, 257/287, 257/408, 257/410, 257/295, 257/411, 257/412, 257/402
• US Class Current: 257/288
• CPC Class Codes: H01L 21/26513 of electrically active species
• CPC Class Codes: H01L 21/2658 of a molecular ion, e.g. decaborane
• CPC Class Codes: H01L 21/28035 the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities H01L21/28105 takes precedence
• CPC Class Codes: H01L 21/28167 on single crystalline silicon, e.g. using a liquid, i.e. chemical oxidation
• CPC Class Codes: H01L 21/28247 passivation or protection of the electrode, e.g. using re-oxidation
• CPC Class Codes: H01L 21/324 Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering H01L21/20 - H01L21/288 and H01L21/302 - H01L21/322 take precedence
• CPC Class Codes: H01L 21/823807 with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
• CPC Class Codes: H01L 21/823842 gate conductors with different gate conductor materials or different gate conductor implants, e.g. dual gate structures
• CPC Class Codes: H01L 29/1083 with an inactive supplementary region, e.g. for preventing punch-through, improving capacity effect or leakage current
• CPC Class Codes: H01L 29/4925 with a multiple layer structure, e.g. several silicon layers with different crystal structure or grain arrangement with only a vertical doping structure or vertical doping variation H01L29/4916
• CPC Class Codes: H01L 29/517 the insulating material comprising a metallic compound, e.g. metal oxide, metal silicate H01L29/518 takes precedence
• CPC Class Codes: H01L 29/665 using self aligned silicidation, i.e. salicide formation of conductive layers comprising silicides H01L21/28518
• CPC Class Codes: H01L 29/66545 using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
• CPC Class Codes: H01L 29/6659 with both lightly doped source and drain extensions and source and drain self-aligned to the sides of the gate, e.g. lightly doped drain [LDD] MOSFET, double diffused drain [DDD] MOSFET
• CPC Class Codes: H01L 29/7845 the means being a conductive material, e.g. silicided S/D or Gate

Abstract

A method of fabricating a semiconductor device structure, includes: providing a substrate, providing an electrode on the substrate, forming a recess in the electrode, the recess having an opening, disposing a small grain semiconductor material within the recess, covering the opening to contain the small grain semiconductor material, within the recess, and then annealing the resultant structure.

Claims

1. A semiconductor device structure, comprising:

a first semiconductor device having a first gate stack, and

a second semiconductor device having a second gate stack;

wherein said first gate stack includes a first semiconductor material having an average grain size of less than approximately 30 nm, and wherein said second gate stack includes a second semiconductor material having an average grain size of greater than approximately 30 nm, said structure further comprising a first channel disposed below said first gate stack, and a second channel disposed below said second gate stack;

wherein the second gate stack imparts a compressive stress to the second channel in a range of approximately −

200 MPa to approximately −

600 MPa, while the first gate stack imparts a compressive stress to the first channel in a range of approximately −

10 MPa to approximately −

100 MPa.

2. The structure as claimed in claim 1, wherein said first semiconductor material is a grained polysilicon.

3. The structure as claimed in claim 1, wherein said first semiconductor device is an FET and said second semiconductor device is a pFET.

4. The structure as claimed in claim 1, further comprising an isolation region disposed between said first semiconductor device and said second semiconductor device.

5. The structure as claimed in claim 1, wherein said second semiconductor material is a grained polysilicon.

6. The structure as claimed in claim 1, further comprising a third semiconductor material and a fourth semiconductor material, wherein said first semiconductor material is disposed on said third semiconductor material and wherein said second semiconductor material is disposed on said fourth semiconductor material.

7. The structure as claimed in claim 6, wherein said third semiconductor material is a small grained polysilicon and said fourth semiconductor material is a small grained polysilicon.